63 Microarchitecture Jobs - Page 2

Job Overview With 125 Arm-powered products shipped every second, we&aposll be in a over a trillion smart devices by 2035. Your smartphone, award-winning VR gaming, the world&aposs fastest supercomputer our engineers are designing the advanced core processors leading the race towards a connected, autonomous, hyper-performance future. The Architecture and Technology Group (ATG) at Arm develops technologies and products for Arms future architecture roadmap. Architecture Verification product group develops Architecture Compliance Kits that are used by multiple development teams to validate that implementations are compliant to the Arm architecture specification. This role gives you an opportunit...

As an RTL Engineering Lead at Google, you will play a vital role in driving innovation and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will be instrumental in shaping the future of hardware experiences that cater to millions of users worldwide. By leveraging your expertise, you will enhance performance, efficiency, and integration in the next generation of Google products. With a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience, along with 6 years of hands-on experience in micro-architecture and coding, particularly in memory compression, interconnects, coherence, cache, Dynamic Random-Acces...

We are seeking a highly skilled Physical Design Engineer to own the RTL to GDS physical implementation flows for high-performance and low-power designs. You will be responsible for synthesis, floor-planning, place and route, clock tree synthesis, timing and power closure, EM/IR, PDV, and final PD sign-off. This role requires deep collaboration with micro-architects, expertise in physical design tools, and a strong understanding of modern sub-micron technology nodes. Roles and Responsibility: Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV, and final PD sign off. Own physical design & impleme...

We are seeking a highly skilled Microarchitect and RTL Design Engineer to design and develop microarchitectures for highly configurable IPs, ensuring optimal performance, power, and area. You will collaborate with software and verification teams on various aspects of the design lifecycle, from defining configuration requirements to debugging and coverage. This role requires extensive hands-on experience in microarchitecture and RTL development, proficiency in Verilog/SystemVerilog, and an in-depth understanding of on-chip interconnects and NoCs. Roles and Responsibilities: Design and develop microarchitectures for a set of highly configurable IPs. Perform microarchitecture and RTL coding , e...

You will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Additionally, you will participate in defining the architecture and microarchitecture features of the block being designed. You will apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals, as well as design integrity for physical implementation. It will be your responsibility to review the verification plan and implementation to ensure design features are verified...

You will be part of a highly skilled and challenging high-speed parallel PHY design team, focusing on DDR, LPDDR, and other similar interfaces. Your responsibilities will include designing and developing high-speed interface PHY and its sub-blocks, such as data paths, analog calibration, training, IP initialization, low power control, test, and loopback. You will be involved in various aspects of design and verification from specification to silicon, including interface design for controllers and SoCs. Actively participate in problem-solving and implementing improvements, as well as mentoring and coaching other design team members on technical issues. Collaborate with Analog designers to ens...

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You wi...

As an experienced professional in ASIC development with a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, you will be leading a team of engineers in Bengaluru to deliver AI/ML compute intensive IPs and subsystems. With 8 years of experience in Verilog/SystemVerilog, VHDL, or Chisel, and 4 years of people management expertise, you will collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. Your responsibilities will include taking ownership of complex IPs or subsystems, implementing RTL, and driving design methodology, libraries, debug, and code review in coordi...

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. You...

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System ...

Responsibilities: In this role, he/she would be the technical lead responsible for driving design, quality and debug throughput of top-level development and support post-silicon debugs. Working with architects and verification leads and driving quality microarchitecture specifications. Developing design infrastructure and needed improvements Developing design strategy for quality. Driving design closure to meet schedule with quality Working with each domain (sub-system) lead and guide them to get better quality and design outcome. Helping management with risk assessment on features, quality, and schedules Working with sub-system design leads to identify potential areas of formal verification...

The job is located in Bangalore and requires 3-5 years of experience for 2 available positions. The primary responsibility involves RTL Design, with a focus on practical experience in RTL development using VHDL and/or Verilog. This includes functional and structural RTL design, design partitioning, simulation, regression, and collaboration with design verification teams. The ideal candidate should be familiar with the latest RTL languages and tools such as Modelsim, VCS, Design Compile, Prime Time, Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, among others. Desirable experience includes strong processor architecture knowledge, microarchitecture implementation, micro...

You will be part of a highly skilled and challenging high-speed parallel PHY design team, working on DDR, LPDDR, and other similar projects. Your responsibilities will include designing and developing high-speed interface PHY and its sub-blocks, such as high-speed data paths, analog calibration, training, IP initialization, low power control, test, and loopback functionalities. You will be accountable for various aspects of design and verification starting from specification to silicon, along with interface design for controllers and SoCs. Your active involvement in problem-solving and identifying opportunities for improvement will be crucial. Additionally, you will be mentoring and coaching...

You should have at least 8 years of experience in Micro-architecture, SoC development, and full-chip design for multi-million gate SoCs. Your expertise should include a strong understanding of the design convergence cycle, encompassing architecture, micro-architecture, Verification, Synthesis, and timing closure. You should also be adept at managing IP dependencies and planning front-end design tasks effectively. Additionally, you should have experience in designing and developing high-speed serial IO protocols. Your skills should cover the implementation of clock rate compensation FIFO, gearbox design for data width, bypass on controller, power gating, and low power modes. Experience in CPU...

You are invited to join Lattice Semiconductor as a SoC RTL Design Engineer in Pune, India. Lattice is a global community of engineers, designers, and specialists working in collaboration with sales, marketing, and support teams to develop cutting-edge programmable logic solutions that are revolutionizing the industry. As a SoC RTL Design Engineer at Lattice Semiconductor, you will be part of a dynamic team dedicated to IP design and full chip integration. This role offers ample opportunities to contribute, learn, innovate, and grow within a fast-paced and results-oriented environment. Key responsibilities of this role include working on FPGA projects, RTL design, SoC integration, and ensurin...

You will be joining Qualcomm India Private Limited as a Sub-System Hardware Architect specializing in ASIC design for AI within the Engineering Group > Hardware Engineering. Your primary responsibility will be to define and lead the hardware architecture for ASIC components within the Turing subsystem, ensuring they meet performance, reliability, power, and scalability requirements. You should have proven experience in designing ASIC sub-system hardware components for AI applications, strong knowledge of ASIC design tools and methodologies, and excellent problem-solving skills. Your role will involve collaborating with cross-functional teams to define hardware requirements, developing and im...

As an experienced VLSI SoC RTL designer with 10 to 15 years of work experience, you will play a crucial role in securing an optimal digital IP and circuit. Your responsibilities will include designing and verifying functions in alignment with the required goals. You will have the opportunity to contribute to various areas such as SoC Clock/reset, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU, Host Subsystem, and Flash Subsystem based on your skills and interests. To excel in this role, you should have a strong understanding of digital design principles, with specific knowledge of AMBA SoC BUS protocols like APB, AXI, and AHB. Your tasks will involve creating micro-architecture and de...

You will be responsible for RTL ASIC front end design with Microarchitecture and Verilog coding. Your tasks will include MAS development, RTL coding, development of modules, and feature additions. You should have experience in working with medium complexity protocols and be well-versed in slow-speed protocols like I2C, SPI, and UART. Familiarity with AMBA bus protocols (APB, AHB, AXI) is required. Additionally, you should have experience in Quality check flows, including lint and CDC. For candidates with 8+ years of experience, you are expected to be very strong in RTL coding. Your role will involve microarchitecture development, owning and delivering a subsystem or top level in a SoC projec...

As a Senior ASIC RTL Design Engineer at Google, you will be a key member of a team dedicated to creating custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions globally. Your expertise will play a crucial part in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. As part of the Devices & Services team, you will have the opportunity to combine the best of Google AI, Software, and Hardware to create innovative ...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. You should possess at least 5 years of experience in ASIC development with Verilog/SystemVerilog and VHDL. It is essential to have experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Additionally, experience in micro-architecture and design of subsystems is required. Preferred qualifications: Ideally, you should have experience in SoC designs and integration flows. Proficiency in scripting languages such as Python or Perl would be beneficial. Knowledge of high performance and low p...

As a member of Micron Technology's innovative memory and storage solutions team, you will be part of a dynamic group dedicated to transforming information into intelligence, inspiring advancements in learning and communication. Specifically, you will contribute your expertise to a high-speed parallel PHY design team, focusing on DDR, LPDDR, and other related technologies. Your responsibilities will include designing and developing high-speed interface PHY components, such as data paths, analog calibration, training algorithms, IP initialization, low power control, and more. You will play a crucial role in various aspects of design and verification, from specification to silicon implementatio...

Qualcomm India Private Limited is seeking a skilled individual to join their Engineering Group in the Hardware Engineering department. As a part of the team, you will be responsible for defining the Debug Enabling Tools Strategy for the next generation CPU product line before design execution. This includes defining the DFD Hardware Validation Strategy, aligning with customers and architecture/micro-architecture teams, estimating efforts, identifying equipment and platform requirements, and ensuring the overall validation scope is met. You will also drive the DFD Domain by defining validation coverage metrics across all validation teams engaged from HW design through post-silicon and beyond....

Key Responsibilities: Hands-on microarchitecture and RTL development for IP blocks Develop microarchitecture based on design specifications, including HW-SW interface definition IP-level verification and debugging for video and audio subsystems Work on MIPI CSI and DSI protocols understanding at protocol and implementation level Collaborate with design, verification, and software teams to ensure high-quality deliverables Drive or contribute to test plan creation, environment development, and coverage closure

Job Title: SoC Design lead/manager Expectation: 12+ Years of relevant industry experience in multiple SoC designs Strong technical background in driving SoC design independently Experience in processor system integration, NoC design and integration, Good understanding of high-speed protocols such as PCIe/DDR/HBM/Ethernet etc.. Strong experience with AXI/AHB bus protocols. Defining sign-off quality design constraints for SoC. Hands-on expertise with low-power design techniques such as UPF/CPF. Experience in Security aspects in SoC [secure JTAG, encryption/decryption] &secure boot design. Experience in Lint/CDC checks Hand-on experience in Verilog HDL, System Verilog, C/C++ Drive one or more t...

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on ...