ASIC RTL Design Manager, Silicon

**Job Description:** **Role Overview:** You will be part of a team that is dedicated to pushing boundaries and developing custom silicon solutions for Google's direct-to-consumer products. Your contribution will play a crucial role in shaping the next generation of hardware experiences, ensuring unparalleled performance, efficiency, and integration for products loved by millions worldwide. **Key Responsibilities:** - Lead a team in delivering fabric interconnect design. - Develop and refine RTL design to meet power, performance, area, and timing goals. - Define details such as interface protocol, block diagram, data flow, and pipelines. - Oversee RTL development and debug functional/performance simulations. - Collaborate effectively with multi-disciplined and multi-site teams. **Qualifications Required:** - Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. - 15 years of experience in ASIC RTL design. - Experience with RTL design using Verilog/System Verilog and microarchitecture. - Experience with ARM-based SoCs, interconnects, and ASIC methodology. **About the Company:** Google's mission is to organize the world's information and make it universally accessible and useful. The Devices & Services team at Google combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. They focus on researching, designing, and developing new technologies and hardware to enhance user interactions with computing, making it faster, seamless, and more powerful. The team's efforts are directed towards improving people's lives through technology. (Note: The Preferred qualifications section is omitted as it does not contain any specific details relevant to the job description.),