ASIC RTL Design Manager, Silicon

As a Senior ASIC RTL Design Engineer at Google, you will play a crucial role in shaping the future of custom silicon solutions that drive Google's direct-to-consumer products. Your expertise in RTL design will be instrumental in delivering innovative hardware experiences with superior performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience, and a minimum of 15 years of experience in ASIC RTL design, you are well-equipped to excel in this role. Your proficiency in Verilog/System Verilog and microarchitecture will be essential in contributing to the development of ARM-based SoCs, interconnects, and ASIC methodology. In addition to your technical skills, having a Master's degree in Electrical Engineering or Computer Engineering will be advantageous. Your experience in driving multi-generational roadmaps for IP development and leading interconnect IP design teams for low power SoCs will further enhance your capabilities. As part of our dynamic team, you will lead a group of talented individuals to deliver fabric interconnect design. Your responsibilities will include developing and optimizing RTL designs to meet power, performance, area, and timing requirements. You will define key details such as interface protocols, block diagrams, data flow, and pipelines while overseeing RTL development and conducting functional/performance simulations. Effective communication and collaboration with cross-functional and multi-site teams will be crucial in ensuring the successful execution of projects. By joining Google's Devices & Services team, you will have the opportunity to contribute to creating revolutionary technologies that enhance user experiences and make a positive impact on people's lives through cutting-edge hardware innovations.,