5 Interconnects Jobs

As an Electrical Engineer or Computer Science professional with a Bachelor's degree and 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon, you will have the opportunity to contribute to the innovation behind Google's direct-to-consumer products. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Your responsibilities will include defining the microarchitecture of IPs, Subsystems, or SOCs, working with cross-functional teams to ensure quality, schedule compliance, and PPA optimized design. You will collaborate with Verification, Design for Test, Physical Design, and Software teams to make design decisions and represent project status throughout the development process. Additionally, you will define block-level design documents such as interface protocols, block diagrams, transaction flows, and pipelines. You will be responsible for RTL coding for SS/SOC integration, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Working with key design collaterals such as SDC and UPF, you will negotiate the right collateral quality and identify solutions in collaboration with stakeholders. Preferred qualifications include a Master's degree or PhD in Electrical Engineering or equivalent practical experience, experience with chip design flow and cross-domain involving DV, DFT, Physical Design, and software. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip-level verification will be advantageous. Knowledge in areas such as Processor Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin-muxing is also beneficial. Join a team that pushes boundaries and works towards developing custom silicon solutions that power the future of Google's products, loved by millions worldwide. Contribute your skills and expertise to create radically helpful experiences by combining the best of Google AI, Software, and Hardware. Be a part of a team that aims to make people's lives better through technology.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions to power Google's direct-to-consumer products. Your role will involve contributing to the innovation that drives the creation of products loved by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. Your responsibilities will include: - Contributing as an ASIC RTL engineer to sub-system and chip-level integration activities. This will involve task planning, conducting code and design reviews, and contributing to sub-system/chip-level integration. - Working closely with the architecture team to develop implementation strategies that meet quality, schedule, and power performance area requirements for sub-system/chip-level integration. - Collaborating with the subsystem team to plan SOC milestones, quality checks, and guide subsystem teams with SOC level requirements such as IPXACT, CSR, Lint, CDC, SDC, UPF, etc. - Engaging with a cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and provide project status updates throughout the development process. To be successful in this role, you should have a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. You should also have at least 3 years of experience in RTL coding using Verilog or SystemVerilog language, with experience in high-performance design, multi-power domains with clocking. Preferred qualifications include experience with multiple SoCs with silicon success, knowledge of ASIC design methodologies for front quality checks, and domain expertise in areas such as Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux. Additionally, an understanding of cross-domain activities involving domain validation, design for testing, physical design, and software will be beneficial. Join us at Google and be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Help us research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to make people's lives better through technology.,

As a software engineer at Google, you will be responsible for developing the next-generation technologies that impact how billions of users connect, explore, and interact with information. Your role will involve working on projects critical to Google's needs, with the opportunity to switch teams and projects as the business evolves. You are expected to bring fresh ideas from various areas such as information retrieval, distributed computing, system design, networking, security, AI, UI design, and more. Your primary responsibilities will include designing, developing, testing, deploying, maintaining, and enhancing software solutions. You will manage project priorities, deadlines, and deliverables. The mission of Google is to organize the world's information and make it universally accessible and useful. Your work will involve combining AI, software, and hardware to create innovative and helpful experiences for users. Minimum qualifications for this role include a Bachelor's degree in Electrical, Electronics, or Computer Engineering, or equivalent practical experience. You should have at least 2 years of experience in development, testing, and deployment of consumer electronics/embedded systems. Proficiency in Embedded Systems, Devices, C, C++, Kernel, Device Drivers, Linux, and Firmware is required. Experience in embedded programming in C/C++ is also necessary. Preferred qualifications include expertise in the Embedded domain, data structures, algorithms, and software design. Experience in collaborating with hardware designers and reading schematics is beneficial. Knowledge of Advanced RISC Machine (ARM) or other low-power SoC architectures, memory systems, interconnects, performance/power analysis, Real-Time Operating System (RTOS) concepts, and device drivers is an added advantage. In this role, you will design software applications for developers, enabling them to utilize hardware accelerators seamlessly and efficiently. You will implement and validate firmware and Linux drivers to optimize power consumption and performance. Additionally, you will design, develop, and test embedded software drivers for the next generation of smart devices. Your responsibilities will also include triaging product or system issues, debugging, tracking, and resolving issues impacting hardware, network, or service operations and quality. Writing product or system development code will be an integral part of your role.,

As a Senior ASIC RTL Design Engineer at Google, you will be a key member of a team dedicated to creating custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions globally. Your expertise will play a crucial part in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. As part of the Devices & Services team, you will have the opportunity to combine the best of Google AI, Software, and Hardware to create innovative and helpful user experiences. You will be involved in researching, designing, and developing new technologies and hardware to enhance user interactions with computing, making them faster, seamless, and more powerful. **Responsibilities:** - Lead a team to deliver fabric interconnect design for ASICs. - Develop and enhance RTL design to meet power, performance, area, and timing objectives. - Define key details such as interface protocols, block diagrams, data flow, and pipelines. - Oversee RTL development and debug functional/performance simulations. - Collaborate effectively with multi-disciplined and multi-site teams. **Minimum Qualifications:** - Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. - 15 years of experience in ASIC RTL design. - Proficiency in RTL design using Verilog/System Verilog and microarchitecture. - Experience with ARM-based SoCs, interconnects, and ASIC methodology. **Preferred Qualifications:** - Master's degree in Electrical Engineering or Computer Engineering. - Proven experience in driving multi-generational roadmap for IP development. - Experience in leading interconnect IP design teams for low power SoCs.,

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production.this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in AI Accelerators DNN Accelerators co-processors Interconnect Fabric Cache Coherency D2D C2C SoC Director Bangalore We are a AI semiconductor startup company headquartered in Ann Arbor, Michigan, with branches in , Taiwan and Bangalore, India. We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for embedded Edge AI vision-based applications and real-time data processing. Company has working HW & SW for customer sampling, with production designs in the pipeline, and a system architecture designed a future of neuromorphic computing. We are backed by excellent VC funding and is currently in a stage of rapid growth. While our tech is one of a kind we would not be able to make these advancements without our team. Our collaborative culture is one of the keys to our success. Who You Are You are an open and honest communicator who values your team You are innovative, enjoy bringing new ideas to the table and are receptive to ideas and feedback from others Youre passionate about advancing the state of the world through new technology You enjoy the ambiguity and pace of a startup environment The role This leadership role will be responsible for the global VLSI efforts at and India Site Management. It is a highly visible role reporting to Senior Director with ownership of all pre/post Si activities, leading interface with external EDA, IP, Design Service partners, managing the India site operations and a global VLSI team. What you will be doing: Ownership of pre-Si Design of the next-gen AI accelerator at driving deliverables with Design and IP Service providers, CAD tools, IPs, DFT/PD/Packaging and Test. Work closely with internal Architecture, SW, Emulation, and system board designers on product definition, microarchitecture, and design implementation. Build and manage the VLSI team of front-end design and verification engineers across India and Taiwan. Establish best practices for development, testing, reviews, and documentation. Participate in strategic discussions for product features and roadmap. What we expect to see: BS/MS in Electrical/Electronic Engineering with 18+ years of experience in VLSI, SOC design, several Si tape-out/production. Hands-on experience in front-end design, VLSI flows, and working experience for all aspects of Si tape-out, post-Si validation. Self-driven, organized with strong leadership and communication skills. Experience in building and managing teams with the ability to motivate and lead in a startup environment. Proven track record in several successful productizations. What we would be happy to see: Knowledge of AI, specifically Deep Neural Networks Application-specific accelerators or co-processors Startup experience Site Leadership experience Reports to: Site Lead Work location: Bangalore, India Hours: Full time Employment Opportunity and Benefits of Employment: We are committed to creating and fostering a diverse and inclusive workplace environment for all of our employees. We are an equal opportunity employer. Contact: Uday Mulya Technologies Email: muday_bhaskar@yahoo.com