17 Interconnects Jobs

**Job Description** **Role Overview:** In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. **Key Responsibilities:** - Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. - Identify and write all types of coverage measures for stimulus and corner-cases. - Debug tests with design engineers to deliver functionally correct design blocks. - Measure to identify verification holes and to show progress towards tape-out. - Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). **Qualifications Required:** - Bachelor's degree in Electrical Engineering or equivalent practical experience. - 4 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. - Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired. - Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). **About the Company:** The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.,

Job Description: You will be responsible for leading the configuration, maintenance, and optimization of the organization's network and security infrastructure to ensure high performance and reliability. Your key responsibilities will include: - Architecting and integrating networks across multiple business units and diverse cloud environments, ensuring seamless connectivity and scalability. - Championing the use of Infrastructure as Code processes to automate and maintain infrastructure consistency, scalability, and up-to-date configurations. - Overseeing the configuration, deployment, and management of F5 Local Traffic Managers (LTMs) and Advanced Security Modules (ASMs) to ensure seamless application delivery and security. - Creating and implementing strategies for integrating cloud Virtual Private Clouds (VPCs), interconnects, and direct connects, ensuring efficient and secure data flow between on-premises and cloud environments. - Proactively identifying opportunities to enhance the network's scalability and resilience, ensuring it can handle growing business demands and traffic loads. - Working closely with infrastructure, application, and security teams to ensure network designs meet cross-functional requirements and adhere to best practices. Qualifications Required: - Minimum of 8 years of relevant work experience and a Bachelor's degree or equivalent experience. Company Details: Our beliefs are the foundation for how we conduct business every day. We live each day guided by our core values of Inclusion, Innovation, Collaboration, and Wellness. Together, our values ensure that we work together as one global team with our customers at the center of everything we do and they push us to ensure we take care of ourselves, each other, and our communities. If you want to learn more about our culture and community, you can visit https://about.pypl.com/who-we-are/default.aspx.,

As an Electrical Engineer with 4 years of experience in Verification, you will play a crucial role in shaping the future of AI/ML hardware acceleration. Your responsibilities will include driving cutting-edge TPU (Tensor Processing Unit) technology for Google's demanding AI/ML applications. You will be part of a dynamic team that focuses on developing custom silicon solutions to power Google's TPU, contributing to innovative products loved by millions worldwide. Your key responsibilities will involve: - Planning the verification of digital design blocks and collaborating with design engineers to identify critical verification scenarios. - Identifying and implementing various coverage measures for stimulus and corner-cases to ensure thorough verification. - Debugging tests with design engineers to ensure the delivery of functionally correct design blocks. - Creating a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Preferred qualifications for this role include a Master's degree in Electrical Engineering or a related field, experience with industry-standard simulators and regression systems, as well as familiarity with AI/ML Accelerators or vector processing units. Excellent problem-solving and communication skills will be essential for success in this role. About the company: The ML, Systems, and Cloud AI (MSCA) organization at Google focuses on designing, implementing, and managing hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. With a commitment to security, efficiency, and reliability, the organization drives innovation in hyperscale computing, including Google Cloud's Vertex AI platform. In this role, you will have the opportunity to own the full verification life-cycle, from planning and test execution to coverage closure, with a specific emphasis on meeting stringent AI/ML performance and accuracy goals. By collaborating closely with design and verification engineers, you will contribute to verifying complex digital designs, particularly focusing on TPU architecture integration within AI/ML-driven systems.,

As an FPGA Architect at NEC Corporation India Pvt. Ltd, you will be responsible for designing and implementing high-performance FPGA designs for wireless communication and aerospace systems. You will conduct research and development activities related to logical synthesis, netlist partitioning, placement, and routing optimizations for FPGA prototyping. Your role will involve optimizing FPGA designs for latency, throughput, power, performance, and area efficiency. Additionally, you will evaluate and select appropriate technologies and tools to support the development process, collaborating with cross-functional teams to align on product requirements and technical specifications. You should possess a BE/B.Tech/M.E/M.Tech or equivalent qualification with at least 12 years of experience in the field. Strong knowledge of SoC architecture, including CPU, GPU, memory hierarchy, interconnects, and accelerators is essential. Hands-on experience in hardware simulators, SoC design, RTL coding in Verilog/VHDL, and advanced digital verification methodology is required. Prior experience in integrating various components such as Nios, MPIS, MicroBlaze, ARM Cortex, GTX/GTH transceivers, and 10GE MAC/DMA controller/PCIe is preferred. Familiarity with EDA tools like Xilinx Vivado, SystemGenerator, ModelSim/QuestaSim, and proficiency in MATLAB and Python for modeling, simulation, and analysis are also desired. In this role, you will be responsible for improving or developing new products, components, equipment, systems, technologies, or processes. This may involve ensuring that research and design methodologies meet established scientific and engineering standards, formulating business plans and budgets for product development, analyzing quality/safety test results for compliance, and staying updated on industry developments for organizational and customer benefit. You may also be involved in technical presentations, monitoring product development outcomes, and managing product regulatory approval processes. As a senior-level professional, you will apply advanced knowledge and work independently to achieve results in overseeing and managing projects/processes with limited supervision. You will face difficult and sometimes complex problems, coaching and reviewing the work of lower-level professionals. NEC Corporation, a global leader in IT and network technologies with over 123 years of expertise, is committed to empowering people, businesses, and society. NEC India has been instrumental in India's digitization journey for the past 70 years, offering diverse solutions across various sectors. Headquartered in New Delhi, NEC India has a nationwide presence with branches in Ahmedabad, Bengaluru, Chennai, Mumbai, Noida, and Surat. The company specializes in IT & Networking Solutions, Unified Communication Solutions, Safety and Security Solutions, Integrated Retail Solutions, Data Centre Solutions, Safe and Smart City Solutions, Transportation Solutions, SDN Solutions, Carrier Telecom Solutions, and Solutions for Society. By deploying cutting-edge technology, NEC India aims to make lives easier, safer, and more productive for all, contributing to a brighter future.,

As a member of the team at this organization, you will play a crucial role in the development of custom silicon solutions that will drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process that leads to the creation of products that are beloved by millions around the globe. Your expertise will be key in shaping the next generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, and a minimum of 3 years of experience in Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture, and automation, you are well-equipped to excel in this role. Additionally, you should have 3 years of experience with Register-Transfer Level quality check tool flows such as Lint, Clock Domain Crossing, Reset Domain Crossing, and Synthesis. Preferred qualifications include experience with methodologies for RTL quality checks, IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols, and ASIC methodology. Additionally, experience with methodologies for low power estimation, timing closure, synthesis, and knowledge in areas such as Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin Multiplexing would be advantageous. Your responsibilities will involve defining microarchitecture details for the integration of Intellectual Property's (IPs) at the macro/Sub-System Workload Requirements Plan (SSWRP) level. You will be engaged in RTL development using SystemVerilog, debugging functional/performance simulations, and conducting RTL quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, and Unified Power Format (UPF) checks. Furthermore, you will participate in synthesis, timing/power estimation, and FPGA/silicon bring-up processes. Join us in our mission to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create experiences that are radically helpful. By researching, designing, and developing new technologies and hardware, we aim to make computing faster, seamless, and more powerful, ultimately improving people's lives through technology.,

Qualcomm India Private Limited is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation towards creating a smarter, connected future for all. As a Qualcomm Systems Engineer, your responsibilities will include researching, designing, developing, simulating, and validating systems-level software, hardware, architecture, algorithms, and solutions to facilitate the development of cutting-edge technology. Collaboration across functional teams is essential to meet and exceed system-level requirements and standards. Minimum Qualifications: - Bachelor's degree in Engineering, Information Systems, Computer Science, or related field with 3+ years of Systems Engineering or related work experience, or - Master's degree in Engineering, Information Systems, Computer Science, or related field with 2+ years of Systems Engineering or related work experience, or - PhD in Engineering, Information Systems, Computer Science, or related field with 1+ year of Systems Engineering or related work experience. You will be a part of the Automotive System Performance team, focusing on optimizing Multimedia performance on Snapdragon Automotive chipsets. The ideal candidate should possess a minimum of 6-8 years of experience in Multimedia technologies including Camera, Video, Graphics, and Display technologies. Proficiency in Android/Linux kernel fundamentals, Debug tools, interconnects, System QoS, Bus protocols, and performance Monitoring is required. Key Requirements: - 6-8 years of embedded domain experience in Multimedia Hardware architecture and device driver development. - Proficient in hardware fundamentals of display/Video/Camera basics, DDR, SMMU, NOC, system interconnects, AXI/AHB Bus protocols, and hardware Performance Monitoring systems. - Good understanding of Auto/Mobile SoC architectures and Multimedia Subsystems hardware data flows. - Basics of Arm processor architecture, Multicore/Multiprocessor with SMP/heterogeneous cores. Expertise in C programming language on an embedded platform. - Operating systems/RTOS/Linux kernel internals, scheduling policies, locking mechanism, MMU/paging, etc. - Prior working experience in IP hardware functional and performance validation in silicon and/or emulation, preferably in Multimedia domain. - Familiarity with Android System tools, Debug tools, JTAG, scripting, etc. - Passion for debugging system-level issues, collaborating with teams across geographies, and working towards meeting project milestones. - Exposure to working on emulation/pre-si environment is an added advantage. Responsibilities include assuming all project execution responsibilities, supporting activities related to System use cases profiling and optimization, and understanding HW setups in the lab to carry out performance tests. Education Requirements: - Required: Bachelor's in Computer Engineering and/or Computer Science and/or Electrical Engineering - Preferred: Master's in Computer Engineering and/or Computer Science and/or Electrical Engineering Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Employees are expected to adhere to all applicable policies and procedures, including those concerning security and protection of Company confidential information. Qualcomm does not accept unsolicited resumes or applications from agencies and urges individuals seeking a job at Qualcomm to use the Careers Site for applications.,

As a Senior ASIC RTL Design Engineer at Google, you will play a crucial role in shaping the future of custom silicon solutions that drive Google's direct-to-consumer products. Your expertise in RTL design will be instrumental in delivering innovative hardware experiences with superior performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience, and a minimum of 15 years of experience in ASIC RTL design, you are well-equipped to excel in this role. Your proficiency in Verilog/System Verilog and microarchitecture will be essential in contributing to the development of ARM-based SoCs, interconnects, and ASIC methodology. In addition to your technical skills, having a Master's degree in Electrical Engineering or Computer Engineering will be advantageous. Your experience in driving multi-generational roadmaps for IP development and leading interconnect IP design teams for low power SoCs will further enhance your capabilities. As part of our dynamic team, you will lead a group of talented individuals to deliver fabric interconnect design. Your responsibilities will include developing and optimizing RTL designs to meet power, performance, area, and timing requirements. You will define key details such as interface protocols, block diagrams, data flow, and pipelines while overseeing RTL development and conducting functional/performance simulations. Effective communication and collaboration with cross-functional and multi-site teams will be crucial in ensuring the successful execution of projects. By joining Google's Devices & Services team, you will have the opportunity to contribute to creating revolutionary technologies that enhance user experiences and make a positive impact on people's lives through cutting-edge hardware innovations.,

You will need a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. It is essential to have experience in verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or C/C++. Additionally, you should have experience with verification components and environments in standard verification methodology, as well as experience in verifying digital systems using standard Internet Protocols (IP) components/interconnects. Familiarity with coding languages and software development frameworks is also required. A Master's degree in Electrical Engineering or Computer Science, or a PhD in Electrical Engineering or Computer Science, or equivalent practical experience is preferred. Candidates with an architectural background in Hierarchies, Coherency, Memory Consistency Models, Peripheral Component Interconnect Express (PCIe), Packet Processors, Security, or Clock and Power Controllers will be given preference. Experience with building verification methodologies that span simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is also desirable. Additionally, experience with performance verification of System on a Chip (SOCs), pre-Silicon analysis, and post-Silicon correlation, as well as familiarity with Interconnect Protocols, is a plus. As part of the team developing custom silicon solutions for Google's direct-to-consumer products, you will have the opportunity to contribute to innovative products with a global reach. Your role will involve shaping the next generation of hardware experiences, focusing on delivering exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. By combining the best of Google AI, Software, and Hardware, our team strives to create profoundly helpful experiences through research, design, and development of new technologies and hardware. Your responsibilities will include planning and executing the verification of the next generation configurable Infrastructure Internet Protocols (IPs), interconnects, and memory subsystems. You will be expected to create and enhance constrained-random verification environments using SystemVerilog, develop cross-language tools and scalable verification methodologies, identify and write various coverage measures for stimulus and corner-cases, and collaborate with design engineers to debug tests and deliver functionally correct blocks and subsystems. Closing coverage measures to identify verification gaps and demonstrate progress towards tape-out will also be part of your role.,

The ideal candidate for this role should have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Additionally, a minimum of 10 years of experience in creating and utilizing verification components and environments in standard verification methodology is required. Experience in verifying digital systems using standard IP components/interconnects such as microprocessor cores and hierarchical memory subsystems is also essential. Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture. Candidates should also have experience in low-power design verification, as well as familiarity with Interconnect Protocols like AHB, AXI, ACE, CHI, CCIX, and CXL. Furthermore, expertise in Architectural backgrounds related to Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock, and Power Controllers is advantageous. As a member of the team, you will be involved in developing custom silicon solutions that drive Google's direct-to-consumer products. Your contributions will play a crucial role in shaping innovative products that are cherished by millions globally. Your skills and knowledge will influence the future of hardware experiences, ensuring exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. By combining Google AI, Software, and Hardware expertise, our team creates groundbreaking experiences that are incredibly beneficial. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power. Our ultimate goal is to enhance people's lives through innovative technology solutions. Key Responsibilities: - Verify designs using advanced verification techniques and methodologies. - Collaborate across functions to troubleshoot failures and validate the functional accuracy of designs. - Develop comprehensive test plans encompassing verification strategy, environment, components, stimulus, checks, and coverage, ensuring user-friendly documentation. - Lead the verification of next-generation configurable Infrastructure IPs, interconnects, and memory subsystems. - Collaborate with design engineers to debug tests and deliver functionally sound blocks and subsystems. Monitor coverage metrics to pinpoint verification gaps and demonstrate progress towards tape-out.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions worldwide. Your expertise will play a crucial role in shaping the next generation of hardware experiences, focusing on delivering unparalleled performance, efficiency, and integration. In this role, you will lead a team of ASIC RTL engineers, overseeing sub-system and chip-level integration activities. Your responsibilities will include planning tasks, conducting code and design reviews, and developing complex features. You will collaborate closely with the architecture team to develop implementation strategies that meet quality, schedule, performance, power, and area requirements for sub-system/chip-level integration. Additionally, you will work with a cross-functional team comprising Verification, Design for Test, Physical Design, and Software teams. Your role will involve making design decisions and representing project status throughout the development process. Your contributions will be essential in ensuring the successful execution of projects and meeting the goals set for each stage of development. If you have a Bachelor's degree in Electrical Engineering or Computer Science, along with 8 years of experience in high-performance design and multi-power domains with clocking, and have worked on multiple SoCs with silicon success, this role could be an exciting opportunity for you. Experience with Verilog or System Verilog language is essential, and familiarity with ASIC design methodologies for front quality checks and chip design flow will be advantageous. Join us at Google, where we combine the best of Google AI, Software, and Hardware to create radically helpful experiences. Our mission is to make the world's information universally accessible and useful, and your contributions as an ASIC RTL Engineer will play a significant role in achieving this goal.,

As a Verification Engineer at Google, you will play a crucial role in the development of custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process behind products that are cherished by millions globally. Your expertise will be pivotal in shaping the upcoming generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. Your primary responsibility will involve planning and executing the verification of the next generation configurable Infrastructure Internet Protocols (IPs), interconnects, and memory subsystems. You will be tasked with creating and refining constrained-random verification environments using SystemVerilog, as well as developing cross-language tools and scalable verification methodologies. In this role, you will be expected to identify and implement various coverage measures for stimulus and corner-cases, ensuring comprehensive testing coverage. Collaborating closely with design engineers, you will debug tests to deliver functionally correct blocks and subsystems, while also closing coverage measures to pinpoint verification gaps and showcase progress towards tape-out. To be successful in this position, you should possess a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. Additionally, experience in verifying digital reasoning at the Register-Transfer Level (RTL) using SystemVerilog or C/C++, along with familiarity with verification components and environments in standard verification methodology, is essential. Proficiency in coding languages, software development frameworks, and experience with digital systems using standard Internet Protocols (IP) components/interconnects will be advantageous. Preferred qualifications include a Master's degree or PhD in Electrical Engineering or Computer Science, or equivalent practical experience. A background in architecture with a focus on Hierarchies, Coherency, Memory Consistency Models, and experience with verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes will be beneficial. Additionally, experience with performance verification of Systems on a Chip (SOCs), pre-Silicon analysis, post-Silicon correlation, and Interconnect Protocols would be advantageous. Join our dynamic team at Google, where we combine the best of Google AI, Software, and Hardware to create innovative and helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to improve people's lives through technology.,

As an RTL Engineering Lead at Google, you will play a vital role in driving innovation and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will be instrumental in shaping the future of hardware experiences that cater to millions of users worldwide. By leveraging your expertise, you will enhance performance, efficiency, and integration in the next generation of Google products. With a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience, along with 6 years of hands-on experience in micro-architecture and coding, particularly in memory compression, interconnects, coherence, cache, Dynamic Random-Access Memory controller, and Physical Layer Device, you are well-equipped to excel in this role. Proficiency in Verilog or SystemVerilog language is a must to thrive in this dynamic environment. Ideally, you possess experience in high-performance design, multi-power domains with complex clocking, and have a proven track record of delivering successful SoCs. Your expertise in microarchitecture design and system design will be pivotal in developing highly optimized IPs with excellent Power, Performance, and Area (PPA) metrics. Familiarity with chip design flow and quality checks at the front end, including Lint, CDC/RDC, Synthesis, and Line Echo Cancellation, will further enhance your capabilities. In this role, you will lead a team of RTL engineers, overseeing IP development plan tasks, conducting code and design reviews, and driving the development of complex features within the IP. Collaboration with the architecture team is essential to strategize microarchitecture and coding implementations that align with quality, schedule, and PPA goals. Additionally, you will work closely with cross-functional teams, including Verification, Design for Test, Physical Design, and Software teams, to make informed design decisions and ensure project progress is effectively communicated throughout the development lifecycle. Join our diverse team of passionate individuals who are committed to pushing boundaries and creating innovative solutions that enhance the lives of people globally. Together, we aim to make technology faster, seamless, and more powerful, ultimately realizing Google's mission of organizing the world's information and making it universally accessible and useful.,

As an Electrical Engineer or Computer Science professional with a Bachelor's degree and 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon, you will have the opportunity to contribute to the innovation behind Google's direct-to-consumer products. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Your responsibilities will include defining the microarchitecture of IPs, Subsystems, or SOCs, working with cross-functional teams to ensure quality, schedule compliance, and PPA optimized design. You will collaborate with Verification, Design for Test, Physical Design, and Software teams to make design decisions and represent project status throughout the development process. Additionally, you will define block-level design documents such as interface protocols, block diagrams, transaction flows, and pipelines. You will be responsible for RTL coding for SS/SOC integration, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Working with key design collaterals such as SDC and UPF, you will negotiate the right collateral quality and identify solutions in collaboration with stakeholders. Preferred qualifications include a Master's degree or PhD in Electrical Engineering or equivalent practical experience, experience with chip design flow and cross-domain involving DV, DFT, Physical Design, and software. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip-level verification will be advantageous. Knowledge in areas such as Processor Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin-muxing is also beneficial. Join a team that pushes boundaries and works towards developing custom silicon solutions that power the future of Google's products, loved by millions worldwide. Contribute your skills and expertise to create radically helpful experiences by combining the best of Google AI, Software, and Hardware. Be a part of a team that aims to make people's lives better through technology.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions to power Google's direct-to-consumer products. Your role will involve contributing to the innovation that drives the creation of products loved by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. Your responsibilities will include: - Contributing as an ASIC RTL engineer to sub-system and chip-level integration activities. This will involve task planning, conducting code and design reviews, and contributing to sub-system/chip-level integration. - Working closely with the architecture team to develop implementation strategies that meet quality, schedule, and power performance area requirements for sub-system/chip-level integration. - Collaborating with the subsystem team to plan SOC milestones, quality checks, and guide subsystem teams with SOC level requirements such as IPXACT, CSR, Lint, CDC, SDC, UPF, etc. - Engaging with a cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and provide project status updates throughout the development process. To be successful in this role, you should have a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. You should also have at least 3 years of experience in RTL coding using Verilog or SystemVerilog language, with experience in high-performance design, multi-power domains with clocking. Preferred qualifications include experience with multiple SoCs with silicon success, knowledge of ASIC design methodologies for front quality checks, and domain expertise in areas such as Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux. Additionally, an understanding of cross-domain activities involving domain validation, design for testing, physical design, and software will be beneficial. Join us at Google and be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Help us research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to make people's lives better through technology.,

As a software engineer at Google, you will be responsible for developing the next-generation technologies that impact how billions of users connect, explore, and interact with information. Your role will involve working on projects critical to Google's needs, with the opportunity to switch teams and projects as the business evolves. You are expected to bring fresh ideas from various areas such as information retrieval, distributed computing, system design, networking, security, AI, UI design, and more. Your primary responsibilities will include designing, developing, testing, deploying, maintaining, and enhancing software solutions. You will manage project priorities, deadlines, and deliverables. The mission of Google is to organize the world's information and make it universally accessible and useful. Your work will involve combining AI, software, and hardware to create innovative and helpful experiences for users. Minimum qualifications for this role include a Bachelor's degree in Electrical, Electronics, or Computer Engineering, or equivalent practical experience. You should have at least 2 years of experience in development, testing, and deployment of consumer electronics/embedded systems. Proficiency in Embedded Systems, Devices, C, C++, Kernel, Device Drivers, Linux, and Firmware is required. Experience in embedded programming in C/C++ is also necessary. Preferred qualifications include expertise in the Embedded domain, data structures, algorithms, and software design. Experience in collaborating with hardware designers and reading schematics is beneficial. Knowledge of Advanced RISC Machine (ARM) or other low-power SoC architectures, memory systems, interconnects, performance/power analysis, Real-Time Operating System (RTOS) concepts, and device drivers is an added advantage. In this role, you will design software applications for developers, enabling them to utilize hardware accelerators seamlessly and efficiently. You will implement and validate firmware and Linux drivers to optimize power consumption and performance. Additionally, you will design, develop, and test embedded software drivers for the next generation of smart devices. Your responsibilities will also include triaging product or system issues, debugging, tracking, and resolving issues impacting hardware, network, or service operations and quality. Writing product or system development code will be an integral part of your role.,

As a Senior ASIC RTL Design Engineer at Google, you will be a key member of a team dedicated to creating custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions globally. Your expertise will play a crucial part in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. As part of the Devices & Services team, you will have the opportunity to combine the best of Google AI, Software, and Hardware to create innovative and helpful user experiences. You will be involved in researching, designing, and developing new technologies and hardware to enhance user interactions with computing, making them faster, seamless, and more powerful. **Responsibilities:** - Lead a team to deliver fabric interconnect design for ASICs. - Develop and enhance RTL design to meet power, performance, area, and timing objectives. - Define key details such as interface protocols, block diagrams, data flow, and pipelines. - Oversee RTL development and debug functional/performance simulations. - Collaborate effectively with multi-disciplined and multi-site teams. **Minimum Qualifications:** - Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. - 15 years of experience in ASIC RTL design. - Proficiency in RTL design using Verilog/System Verilog and microarchitecture. - Experience with ARM-based SoCs, interconnects, and ASIC methodology. **Preferred Qualifications:** - Master's degree in Electrical Engineering or Computer Engineering. - Proven experience in driving multi-generational roadmap for IP development. - Experience in leading interconnect IP design teams for low power SoCs.,

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production.this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in AI Accelerators DNN Accelerators co-processors Interconnect Fabric Cache Coherency D2D C2C SoC Director Bangalore We are a AI semiconductor startup company headquartered in Ann Arbor, Michigan, with branches in , Taiwan and Bangalore, India. We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for embedded Edge AI vision-based applications and real-time data processing. Company has working HW & SW for customer sampling, with production designs in the pipeline, and a system architecture designed a future of neuromorphic computing. We are backed by excellent VC funding and is currently in a stage of rapid growth. While our tech is one of a kind we would not be able to make these advancements without our team. Our collaborative culture is one of the keys to our success. Who You Are You are an open and honest communicator who values your team You are innovative, enjoy bringing new ideas to the table and are receptive to ideas and feedback from others Youre passionate about advancing the state of the world through new technology You enjoy the ambiguity and pace of a startup environment The role This leadership role will be responsible for the global VLSI efforts at and India Site Management. It is a highly visible role reporting to Senior Director with ownership of all pre/post Si activities, leading interface with external EDA, IP, Design Service partners, managing the India site operations and a global VLSI team. What you will be doing: Ownership of pre-Si Design of the next-gen AI accelerator at driving deliverables with Design and IP Service providers, CAD tools, IPs, DFT/PD/Packaging and Test. Work closely with internal Architecture, SW, Emulation, and system board designers on product definition, microarchitecture, and design implementation. Build and manage the VLSI team of front-end design and verification engineers across India and Taiwan. Establish best practices for development, testing, reviews, and documentation. Participate in strategic discussions for product features and roadmap. What we expect to see: BS/MS in Electrical/Electronic Engineering with 18+ years of experience in VLSI, SOC design, several Si tape-out/production. Hands-on experience in front-end design, VLSI flows, and working experience for all aspects of Si tape-out, post-Si validation. Self-driven, organized with strong leadership and communication skills. Experience in building and managing teams with the ability to motivate and lead in a startup environment. Proven track record in several successful productizations. What we would be happy to see: Knowledge of AI, specifically Deep Neural Networks Application-specific accelerators or co-processors Startup experience Site Leadership experience Reports to: Site Lead Work location: Bangalore, India Hours: Full time Employment Opportunity and Benefits of Employment: We are committed to creating and fostering a diverse and inclusive workplace environment for all of our employees. We are an equal opportunity employer. Contact: Uday Mulya Technologies Email: muday_bhaskar@yahoo.com