Application-Specific Integrated Circuit (ASIC) Design Verification Engineer

You will need a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. It is essential to have experience in verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or C/C++. Additionally, you should have experience with verification components and environments in standard verification methodology, as well as experience in verifying digital systems using standard Internet Protocols (IP) components/interconnects. Familiarity with coding languages and software development frameworks is also required. A Master's degree in Electrical Engineering or Computer Science, or a PhD in Electrical Engineering or Computer Science, or equivalent practical experience is preferred. Candidates with an architectural background in Hierarchies, Coherency, Memory Consistency Models, Peripheral Component Interconnect Express (PCIe), Packet Processors, Security, or Clock and Power Controllers will be given preference. Experience with building verification methodologies that span simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is also desirable. Additionally, experience with performance verification of System on a Chip (SOCs), pre-Silicon analysis, and post-Silicon correlation, as well as familiarity with Interconnect Protocols, is a plus. As part of the team developing custom silicon solutions for Google's direct-to-consumer products, you will have the opportunity to contribute to innovative products with a global reach. Your role will involve shaping the next generation of hardware experiences, focusing on delivering exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. By combining the best of Google AI, Software, and Hardware, our team strives to create profoundly helpful experiences through research, design, and development of new technologies and hardware. Your responsibilities will include planning and executing the verification of the next generation configurable Infrastructure Internet Protocols (IPs), interconnects, and memory subsystems. You will be expected to create and enhance constrained-random verification environments using SystemVerilog, develop cross-language tools and scalable verification methodologies, identify and write various coverage measures for stimulus and corner-cases, and collaborate with design engineers to debug tests and deliver functionally correct blocks and subsystems. Closing coverage measures to identify verification gaps and demonstrate progress towards tape-out will also be part of your role.,