6 Interconnect Protocols Jobs

As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all As a Qualcomm Systems Engineer, you will research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enables the development of cutting-edge technology Qualcomm Systems Engineers collaborate across functional teams to meet and exceed system-level requirements and standards Minimum Qualifications: Bachelors degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Systems Engineering or related work experience. OR Masters degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. Infra Systems Architect for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. This position will be responsible for Technical leadership role working with SOC architects, DMs and PDMs from early stages of the project to understand new usecases and feature requirements IP baseline selection, area projections and feature negotiations Convert the requirements to solutions and work with Infra IP development teams to flawlessly implement them Point of contact in Product core and architecture meetings in identifying and solving system level issues. Work with performance projection team to define experiments, analyze data, draw conclusions, identify potential problems and drive solutions Work with SoC, Verification, Physical Design, SoC Floorplan and core teams in identifying optimizations and drive them into products. Point of contact for debugging Post Si issues at system level. Preferred Qualifications 15+ years of experience in SOC/IP architecture, micro-architecture and design. Good understanding of SOC. Possesses expertise in 1 or more of the following technical areas: DDR, Security, access control, Interconnects, SMMU, SOC power management, boot, clock/reset, UBWC, Encryption, ECC Understanding of ARM architecture (Coherency, bus interconnects, Security, arch evolution) Good communication and leadership skills; work with minimal supervision Collaborate with internal (Perf, Design and System team) and external (SoC arch, Client Ips) stakeholders in developing solutions Understanding of traffic patterns and BW of different clients a plus Experience with high-performance and low power micro-architecture concepts Experience with Verilog, logic design principles with timing, area and power implications. Experience with scripting languages like Perl/Python/Java for developing proof of concept of the new ideas. Performance: explore high performance strategies and validate that the micro architecture meets targeted performance. Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI. Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification Good Understanding of concurrency, bandwidth, latency and system level aspects Provides direction, mentoring, and leadership from small to medium sized groups. Education Requirements: Bachelors degree in Electrical Engineering required, Masters or Doctorate preferred

You will need a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. It is essential to have experience in verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or C/C++. Additionally, you should have experience with verification components and environments in standard verification methodology, as well as experience in verifying digital systems using standard Internet Protocols (IP) components/interconnects. Familiarity with coding languages and software development frameworks is also required. A Master's degree in Electrical Engineering or Computer Science, or a PhD in Electrical Engineering or Computer Science, or equivalent practical experience is preferred. Candidates with an architectural background in Hierarchies, Coherency, Memory Consistency Models, Peripheral Component Interconnect Express (PCIe), Packet Processors, Security, or Clock and Power Controllers will be given preference. Experience with building verification methodologies that span simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is also desirable. Additionally, experience with performance verification of System on a Chip (SOCs), pre-Silicon analysis, and post-Silicon correlation, as well as familiarity with Interconnect Protocols, is a plus. As part of the team developing custom silicon solutions for Google's direct-to-consumer products, you will have the opportunity to contribute to innovative products with a global reach. Your role will involve shaping the next generation of hardware experiences, focusing on delivering exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. By combining the best of Google AI, Software, and Hardware, our team strives to create profoundly helpful experiences through research, design, and development of new technologies and hardware. Your responsibilities will include planning and executing the verification of the next generation configurable Infrastructure Internet Protocols (IPs), interconnects, and memory subsystems. You will be expected to create and enhance constrained-random verification environments using SystemVerilog, develop cross-language tools and scalable verification methodologies, identify and write various coverage measures for stimulus and corner-cases, and collaborate with design engineers to debug tests and deliver functionally correct blocks and subsystems. Closing coverage measures to identify verification gaps and demonstrate progress towards tape-out will also be part of your role.,

The ideal candidate for this role should have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Additionally, a minimum of 10 years of experience in creating and utilizing verification components and environments in standard verification methodology is required. Experience in verifying digital systems using standard IP components/interconnects such as microprocessor cores and hierarchical memory subsystems is also essential. Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture. Candidates should also have experience in low-power design verification, as well as familiarity with Interconnect Protocols like AHB, AXI, ACE, CHI, CCIX, and CXL. Furthermore, expertise in Architectural backgrounds related to Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock, and Power Controllers is advantageous. As a member of the team, you will be involved in developing custom silicon solutions that drive Google's direct-to-consumer products. Your contributions will play a crucial role in shaping innovative products that are cherished by millions globally. Your skills and knowledge will influence the future of hardware experiences, ensuring exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. By combining Google AI, Software, and Hardware expertise, our team creates groundbreaking experiences that are incredibly beneficial. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power. Our ultimate goal is to enhance people's lives through innovative technology solutions. Key Responsibilities: - Verify designs using advanced verification techniques and methodologies. - Collaborate across functions to troubleshoot failures and validate the functional accuracy of designs. - Develop comprehensive test plans encompassing verification strategy, environment, components, stimulus, checks, and coverage, ensuring user-friendly documentation. - Lead the verification of next-generation configurable Infrastructure IPs, interconnects, and memory subsystems. - Collaborate with design engineers to debug tests and deliver functionally sound blocks and subsystems. Monitor coverage metrics to pinpoint verification gaps and demonstrate progress towards tape-out.,

As a Verification Engineer at Google, you will play a crucial role in the development of custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process behind products that are cherished by millions globally. Your expertise will be pivotal in shaping the upcoming generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. Your primary responsibility will involve planning and executing the verification of the next generation configurable Infrastructure Internet Protocols (IPs), interconnects, and memory subsystems. You will be tasked with creating and refining constrained-random verification environments using SystemVerilog, as well as developing cross-language tools and scalable verification methodologies. In this role, you will be expected to identify and implement various coverage measures for stimulus and corner-cases, ensuring comprehensive testing coverage. Collaborating closely with design engineers, you will debug tests to deliver functionally correct blocks and subsystems, while also closing coverage measures to pinpoint verification gaps and showcase progress towards tape-out. To be successful in this position, you should possess a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. Additionally, experience in verifying digital reasoning at the Register-Transfer Level (RTL) using SystemVerilog or C/C++, along with familiarity with verification components and environments in standard verification methodology, is essential. Proficiency in coding languages, software development frameworks, and experience with digital systems using standard Internet Protocols (IP) components/interconnects will be advantageous. Preferred qualifications include a Master's degree or PhD in Electrical Engineering or Computer Science, or equivalent practical experience. A background in architecture with a focus on Hierarchies, Coherency, Memory Consistency Models, and experience with verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes will be beneficial. Additionally, experience with performance verification of Systems on a Chip (SOCs), pre-Silicon analysis, post-Silicon correlation, and Interconnect Protocols would be advantageous. Join our dynamic team at Google, where we combine the best of Google AI, Software, and Hardware to create innovative and helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to improve people's lives through technology.,

The DCAI and Silicon Eng Team is responsible for delivering leadership Xeon products to cloud and datacenter customers by developing industry-leading x86 core and differentiated IPs. These IPs enhance product performance and competitiveness in both Xeon and AI platforms. The IP design group within DCAI focuses on designing Coherent Fabric IP, Memory controller, NOC, PCIE, and other fundamental building blocks for Xeon server SOCs. We are currently looking for an experienced Senior Micro Architect to design, develop, and implement advanced Digital IO Controllers such as PCIe/CXL/UCIe systems for next-generation data center and AI chips. This role requires a unique blend of architectural expertise and hands-on RTL coding skills to bring cutting-edge designs to life. The ideal candidate will possess a deep understanding of high-speed IOs like PCIe/CXL/UCIe architecture, interconnect protocols, and coherence mechanisms, along with a proven ability to implement these designs at the RTL level. Key Responsibilities: - Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs. - Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks. - Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs. - Collaborate closely with verification teams to create test plans and debug issues during pre-silicon validation. - Work with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems. - Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases. - Mentor junior engineers, contribute to technical reviews, and design documentation. - Stay updated with emerging technologies and trends in PCIe/CXL/UCIe protocols, as well as AI/ML hardware. - Demonstrate strong problem-solving and debugging skills. - Exhibit excellent communication and collaboration abilities. - Ability to manage and prioritize multiple tasks effectively. Qualifications: - Bachelor's degree with 15+ years of experience or Master's degree in Electronics and Computer Engineering with relevant experience of at least 10+ years. This is an Experienced Hire job type located in India, Bangalore, within the Design Engineering Group (DEG) at Intel. DEG is committed to developing best-in-class SOCs, Cores, and IPs that power Intel's products. The team focuses on delivering leadership products through the pursuit of Moore's Law and groundbreaking innovations. This role is eligible for a hybrid work model allowing employees to split their time between working on-site at the assigned Intel site and off-site. Please note that job posting details, such as work model, location, or time type, are subject to change.,

As a Verification Engineer at Google, you will play a crucial role in ensuring the functionality and performance of Google's custom silicon solutions. You will be responsible for verifying digital systems, including infrastructure IP, interconnects, caches, memory management, and system services. Your expertise will be instrumental in shaping the next generation of hardware experiences, delivering unmatched performance, efficiency, and integration. Your responsibilities will include planning and executing the verification of configurable Infrastructure IPs, interconnects, and memory subsystems. You will develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Additionally, you will create cross-language tools and scalable verification methodologies to ensure comprehensive testing coverage. To excel in this role, you should have a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. You should possess experience in verifying digital systems using standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems. Proficiency in Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, and Python is required. Experience in creating and using verification components and environments in standard verification methodology, scripting languages, and software development frameworks is essential. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering or Computer Science, along with 3 years of experience in areas such as Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers. Experience with building verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is advantageous. Knowledge of Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL), performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation is also beneficial. Join our team at Google and be part of the innovation that drives the future of direct-to-consumer products. Your contributions will have a global impact, shaping products loved by millions worldwide. Embrace the opportunity to work on the verification of Google's System on a Chip (SOC) offerings, collaborating with hardware architects and design engineers to deliver cutting-edge hardware experiences. Your role will involve developing performance Virtual IP address (VIPs) for supported protocols, deploying verification stacks across diverse IPs, and building generalized system topology abstractions. Together, we will develop methodologies and tools to tackle complex challenges and advance technology for the betterment of society.,