586 Emulation Jobs

OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. Job Description: As part of the Platform design team, the Design Engineer will be responsible for leading and contributing to the design and delivery of Core Subsystem across multiple SoC generations. With deep experience in RTL design and SoC-level integration, this role is critical for enabling high-performance, low-power, and functionally safe systems across diverse markets. Responsibilities Collaborate with systems architects and microarchitects to define high level, implementable SOC specifications. Own end-to-end IP/Sub-system RTL delivery while analysing and optimising design for power, performance and area (PPA) targets. Lead RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains. Demonstrate strong proficiency with frontend flows, including LINT, CDC, Synthesis, DFT and Static Timing Analysis (STA). Drive the development of robust Safety, Security and Debug architectures for advanced SOCs with multiple interconnects. Design and integrate standard interface protocols like AHB/AXI and memory interfaces like RAM, Flash. Engage cross-functionally with DFT, Physical Design, Verification, Emulation and Validation teams to ensure first time right silicon and on-time project delivery. Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency. Mentor junior engineers, and provide technical leadership and guidance across multiple design projects. Contribute to the innovation quotient of the team via Patents, Industry standard publications etc. Qualifications: Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering with 12+ years of RTL design experience. Proven expertise in Verilog/System Verilog RTL design, integration and microarchitecture. Strong understanding of SOC architecture, AMBA protocols (AXI,AHB,APB), clock/reset domains and memory sub-systems. Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis. Familiarity with formal verification techniques, static/dynamic power checks. Proficiency in scripting and automation using Python. Excellent leadership, communication skills. Experience working with global cross-functional teams. Working knowledge of safety-critical design flows in automotive systems. Knowledge of Automotive Functional Safety ISO26262 is a plus. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers

OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world! Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. Job Description As part of the Platform design team, the Design Engineer will be responsible for leading and contributing to the design and delivery of Core Subsystem across multiple SoC generations. With deep experience in RTL design and SoC-level integration, this role is critical for enabling high-performance, low-power, and functionally safe systems across diverse markets. Responsibilities Collaborate with systems architects and microarchitects to define high level, implementable SOC specifications. Own end-to-end IP/Sub-system RTL delivery while analysing and optimising design for power, performance and area (PPA) targets. Lead RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains. Demonstrate strong proficiency with frontend flows, including LINT, CDC, Synthesis, DFT and Static Timing Analysis (STA). Drive the development of robust Safety, Security and Debug architectures for advanced SOCs with multiple interconnects. Design and integrate standard interface protocols like AHB/AXI and memory interfaces like RAM, Flash. Engage cross-functionally with DFT, Physical Design, Verification, Emulation and Validation teams to ensure first time right silicon and on-time project delivery. Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency. Mentor junior engineers, and provide technical leadership and guidance across multiple design projects. Contribute to the innovation quotient of the team via Patents, Industry standard publications etc. Qualifications Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering with 12+ years of RTL design experience. Proven expertise in Verilog/System Verilog RTL design, integration and microarchitecture. Strong understanding of SOC architecture, AMBA protocols (AXI,AHB,APB), clock/reset domains and memory sub-systems. Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis. Familiarity with formal verification techniques, static/dynamic power checks. Proficiency in scripting and automation using Python. Excellent leadership, communication skills. Experience working with global cross-functional teams. Working knowledge of safety-critical design flows in automotive systems. Knowledge of Automotive Functional Safety ISO26262 is a plus. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future! To discover more, visit st.com/careers

Job Description Sponsorship: GM DOES NOT PROVIDE IMMIGRATION-RELATED SPONSORSHIP FOR THIS ROLE. DO NOT APPLY FOR THIS ROLE IF YOU WILL NEED GM IMMIGRATION SPONSORSHIP (e.g., H-1B, TN, STEM OPT, etc.) NOW OR IN THE FUTURE. Work Arrangement: This role is categorized as hybrid. This means the successful candidate is expected to report to the office three times per week or other frequency dictated by the business. The Role This position is based at GM Technical Centre India - Bengaluru, where our teams focus on manufacturing engineering in Automation. We specialize in designing, developing and operationalizing complex integrated production systems to deliver cost-effective solutions with highest standards of quality. Automation work categorize into 2 types, Execution & Development. During Execution role, The Controls engineer will be primarily responsible for execution of all Controls related projects in various capacities at GM plants across the Globe with respect to Safety, Delivery, Quality, Cost and Performance. In this position the Engineer will perform offline designs and online execution on various new or existing product programs across our portfolio. The incumbent will need to possess a broad technical knowledge, combined with creative and independent thinking and conceptual ability. During Developmental role, the Controls Engineer will be responsible to work along with Regional & Global team/SMEs to develop & maintain engineering standards work related to Hardware/Software templates, e-tools, etc. This position will be based out of GM Technical Center India in Bangalore and involves travel opportunities across different regions for project execution. What You'll Do Supervise and control projects including project scope, issues, risks and schedule. Handle issues to closure. Communicate project status and ensures all internal customers are aware of progress through project meetings, status reports and reviews. Participate in Investment studies, preliminary design discussions for any new or expansion projects. Responsible for inhouse engineering on Hardware designs, software designs, Emulation, Integration & Commissioning at site. If its Turnkey project, Guide & approve Hardware/ Software designs done by contractors for various project in the region. Conduct offline testing & Buyoff at supplier’s site. Implement GM Global tools for design of hardware & software to ensure minimum debug on site. Train suppliers and Engineers of other GM units. Validate designs and provide feedback to Global Centre w.r.t GM standards. Responsible for deploying GM Global standards across all projects. Responsible for training and Integrating Suppliers to enforce to GM standards. Responsible for performing Root cause analysis. Prepare & Share lessons learnt for the projects completed. Coordinate project timing schedule, design deliverables and safety aspects with team. Jointly conduct test runs for equipment at site as per process. Coordination with other units of GM (worldwide) for Global projects. Develop & Maintain components in Emulate 3D (Electrical & Mechanical) Develop Electrical & Mechanical models using Emulate 3D Thorough knowledge of Plant Floor System related to Automation. Additional Job Description Your Skills & Abilities (Required Qualifications) Masters/ bachelor's degree in electrical engineering / Electronics Engineering / Instrumentation Engineering. 3-10 years' experience in any Automotive companies or Software Companies with Automation background. In depth knowledge of control systems and/or control systems in automotive assembly plants Knowledge on PLC, HMI, Drives, Networks along with strong programming skills preferably Rockwell PLC. Project management and site execution skills. Thorough knowledge of Rockwell PLC software, Siemens HMI software as well as interfaces to other controls systems Knowledge of Emulation softwares like Emulate 3D, etc Knowledge of Machine Vision hardwares/softwares (Matrox) Thorough knowledge of PLC hardware and software design and engineering Knowledge of design for health and safety will be helpful Knowledge on equipment selection, cost estimation, material procurement is an advantage Should be able to read Electrical/mechanical drawings, layout and have design capabilities. Acquaintance with Eplan for hardware design and experience on Siemens HMI will be an added advantage. Ability to understand legacy equipment & propose solutions in case of upgradation. Knowledge of interface to upper level systems. Basic Knowledge on programming skills such as XML, C#, J Script, VBA, Python etc.. Knowledge on Robot Programming and troubleshooting, preferably FANUC Robots Knowledge on Robotic applications like spot-welding, arc-welding, dispensing, roller hemming etc. Acquaintance with Robot simulation studies and experience on Robot simulation software will be an added advantage. Robot interface with other equipment (PLC, Line Controller, Other Machines etc). Experience in large BIW projects. Ability to understand electrical and electronic requirements for mechanical equipment’s. What Will Give You A Competitive Edge (Preferred Qualifications) Good communication and interpersonal skills. Quick Learning & functional expertise. Project management and site execution skills Ability to work with intercultural, multi-disciplinary & remote teams to achieve functional goals. Ability to organize, plan, prioritize and execute projects with a keen attention to details. Willingness to travel across regions for executing projects. About GM Our vision is a world with Zero Crashes, Zero Emissions and Zero Congestion and we embrace the responsibility to lead the change that will make our world better, safer and more equitable for all. Why Join Us We believe we all must make a choice every day – individually and collectively – to drive meaningful change through our words, our deeds and our culture. Every day, we want every employee to feel they belong to one General Motors team. Non-Discrimination and Equal Employment Opportunities General Motors is committed to being a workplace that is not only free of unlawful discrimination, but one that genuinely fosters inclusion and belonging. We strongly believe that providing an inclusive workplace creates an environment in which our employees can thrive and develop better products for our customers. We encourage interested candidates to review the key responsibilities and qualifications for each role and apply for any positions that match their skills and capabilities. Applicants in the recruitment process may be required, where applicable, to successfully complete a role-related assessment(s) and/or a pre-employment screening prior to beginning employment. To learn more, visit How we Hire . Accommodations General Motors offers opportunities to all job seekers including individuals with disabilities. If you need a reasonable accommodation to assist with your job search or application for employment, email us or call us at 800-865-7580. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Opentext - The Information Company OpenText is a global leader in information management, where innovation, creativity, and collaboration are the key components of our corporate culture. As a member of our team, you will have the opportunity to partner with the most highly regarded companies in the world, tackle complex issues, and contribute to projects that shape the future of digital transformation. AI-First. Future-Driven. Human-Centered. At OpenText, AI is at the heart of everything we do—powering innovation, transforming work, and empowering digital knowledge workers. We're hiring talent that AI can't replace to help us shape the future of information management. Join us. OPENTEXT OpenText is a global leader in information management, where innovation, creativity, and collaboration are the key components of our corporate culture. As a member of our team, you will have the opportunity to partner with the most highly regarded companies in the world, tackle complex challenges, and contribute to building products that redefine the future of digital transformation. YOUR IMPACT OpenText™ Quality Engineering is creating a next-generation mobile testing platform — a browser-based solution that allows teams to test mobile applications without the need for physical devices. This innovative product will simulate device behaviors across Android and iOS platforms at a system level, revolutionizing how apps are tested at scale. As a Principal Software Engineer, you will lead the architecture and development of this cutting-edge solution, driving deep technical design, contributing to our long-term strategy, and mentoring a high-caliber engineering team. What The Role Offers Lead design and development of a cloud-based mobile testing platform for Android and iOS applications — entirely browser-based. Apply deep Java expertise to build scalable, high-performance backend systems and REST APIs. Leverage experience with iOS and Android internals (not app development) to emulate device behaviours, integrate debugging interfaces, and replicate OS-level testing features. Collaborate closely with product managers, UX teams, and QA to define architecture, scalability needs, and performance goals. Build emulation components that simulate real device conditions such as sensors, memory constraints, UI rendering behavior, and OS responses. Drive DevOps, CI/CD, and container-based deployments using tools like Docker, Kubernetes, and Terraform. Participate in agile ceremonies and take ownership of engineering deliverables, technical debt, and refactoring needs. Influence architectural decisions, conduct deep design reviews, and champion best practices across teams. What You Need To Succeed A degree in Computer Science, Engineering, or a related field — or equivalent practical experience. 15+ years of hands-on experience in enterprise software development using Java, Spring Boot, and microservices architecture. Strong experience in working with iOS and Android operating system internals, debugging tools, SDKs, or device emulators. Experience developing tools/platforms, not mobile applications — preference for candidates who have built developer tools, system simulators, emulators, or test frameworks. Excellent knowledge of browser-based application architecture and modern UI stacks (e.g., ReactJS). Solid experience with cloud-native applications (preferably AWS), and containerization using Docker and Kubernetes. Deep understanding of software engineering best practices, including design patterns, system architecture, code reviews, testing strategies, and CI/CD. Strong verbal and written communication skills and the ability to collaborate effectively with cross-functional teams. OpenText's efforts to build an inclusive work environment go beyond simply complying with applicable laws. Our Employment Equity and Diversity Policy provides direction on maintaining a working environment that is inclusive of everyone, regardless of culture, national origin, race, color, gender, gender identification, sexual orientation, family status, age, veteran status, disability, religion, or other basis protected by applicable laws. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please contact us at hr@opentext.com. Our proactive approach fosters collaboration, innovation, and personal growth, enriching OpenText's vibrant workplace.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Job Title: Director, x86 CPU Cores Performance Verification Location: Bangalore Experience: 20-22 years The Role We are looking for a results-driven and strategic Director of x86 CPU Performance Verification to lead the development, implementation, and scaling of our performance verification strategy across next-gen CPU cores. In this critical leadership role, you will be responsible for managing a world-class team, defining infrastructure and methodology, and ensuring our CPUs meet and exceed their performance targets from early RTL through post-silicon. You’ll work across architecture, design, functional verification, and software teams to bridge performance intent with silicon reality. If you thrive in fast-paced environments, love solving performance bottlenecks, and are passionate about building and mentoring high-impact teams—this is the opportunity for you. We are seeking a visionary and technically accomplished Director of CPU Cores Performance Verification to lead our efforts in verifying and optimizing performance for next generation x86 CPU cores. The ideal candidate will have deep expertise in CPU microarchitecture, performance modeling, and verification, with a strong background in performance infrastructure, emulation, and AI-driven methodologies. The Person You are a visionary leader with deep technical expertise in CPU microarchitecture and performance validation. You combine strong engineering fundamentals with the ability to scale teams and systems. You are comfortable navigating ambiguity, influencing stakeholders across domains, and delivering results under pressure. You lead with empathy, invest in people, and believe that high-performing teams are built on trust, feedback, and a shared sense of purpose. Key Responsibilities Team Leadership Lead and mentor a high-performing team of performance verification engineers. Foster a culture of innovation, technical rigor, and continuous improvement. Provide strategic direction across multiple concurrent verification programs. Program Leadership Define and execute the performance verification strategy for high-performance x86 CPU cores. Collaborate with architecture, u-arch, RTL, performance modeling, firmware, and software teams to define and validate performance KPIs. Ensure timely delivery of simulation/emulation results, and optimization feedback loops. Performance Analysis & Correlation Develop and execute performance verification plans targeting IPC, latency, throughput, and power efficiency. Validate and debug Performance Monitoring Counters (PMC) to ensure accurate performance visibility. Drive correlation between RTL and performance models, ensuring architectural intent is met. Analyze performance bottlenecks using simulation, emulation, and silicon data. Toolchain & Methodology Build and maintain scalable, modular performance verification infrastructure. Lead emulation-based performance setup and debug, enabling early performance validation. Integrate performance regression, profiling, and analysis flows using industry-standard and custom tools. Collaborate with compiler and OS teams to ensure software stack alignment with hardware performance goals. AI-Driven Infrastructure Drive the development of AI/ML-based infrastructure to automate performance analysis, anomaly detection, and efficiency improvements. Leverage data-driven techniques to optimize verification coverage and reduce debug cycles. Cross-Functional Collaboration Partner with x86 architecture, RTL design, physical design, and software teams to ensure performance targets are met. Influence design decisions through data-backed performance insights. Stakeholder Management Align verification goals with business and product roadmaps. Communicate performance status, risks, and trade-offs to executive leadership and stakeholders. Industry Awareness Stay current with trends in CPU architecture, performance modeling, and verification technologies. Evaluate and adopt emerging tools and techniques to maintain a competitive edge. Preferred Experience 20+ years of industry experience with performance modeling and simulation tools (e.g., cycle-accurate simulators, emulators) with strong background in CPU microarchitecture, performance analysis, and system-level performance verification. Proven leadership in managing large, cross-functional engineering teams. Familiarity with PMC DV, latency and throughput validation, emulation platforms, and performance debug flows. Deep understanding of x86 ISA, microarchitecture, and performance metrics. Experience in developing performance test suites, performance triage tools, and simulation/emulation infrastructure. Expertise in performance analysis tools, correlation techniques, and workload optimization. Strong analytical and problem-solving skills with a data-driven mindset. Excellent communication and interpersonal skills. Deep knowledge of modern out-of-order CPU cores, memory subsystems, and performance modeling is a plus. Experience with ML/AI techniques/frameworks for performance triage, infrastructure automation and prediction is a plus. Exposure to high-performance computing (HPC), virtualization, or server-class CPUs. Background in hardware/software co-design and performance-aware compiler optimizations. Familiarity with pre-silicon and post-silicon debug methodologies. Academic Credentials Bachelors/Masters/Ph.D in electrical engineering, Computer Engineering, or related field. LOCATION: Bangalore CTERR1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role We are looking for an experienced engineer to join the SOC Power Modeling team in the AMD Client Computing and Graphics group. This role involves collaboration with multiple engineering teams including SoC architecture definition, IP design, integration/physical design, verification, and platform architecture. Contributions have a direct impact on the power & performance of AMD’s Client products. The Person The candidate should have SOC design process experience from front end to tapeout. The candidate will work closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design data extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Good verbal and written communication skills are helpful for technical discussions with team members across the globe. Key Responsibilities Work with front end RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level. Work with emulation team on power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met. Work with RTL and physical design teams to generate data on design impact from clock and power gating, device type mix and physical implementation options. Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone. Work with design verification in validating low power design features at SoC and IP level. Preferred Experience Experience with Synopsys EDA tools, particularly PtPx/Power Artist. Understanding of hardware emulation process, stimulus and EDA flows. Experience with Tcl and Python based scripting. Experience with UPF. Academic Credentials Master or Bachelor of Science degree in Electrical Engineering. 3+ years of experience. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Description At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us. Overview As a leading global aerospace company, Boeing develops, manufactures, and services commercial airplanes, defense products and space systems for customers in more than 150 countries. As a top U.S. exporter, the company leverages the talents of a global supplier base to advance economic opportunity, sustainability, and community impact. Boeing’s team is committed to innovating for the future, leading with sustainability, and cultivating a culture based on the company’s core values of safety, quality, and integrity. Technology for today and tomorrow The Boeing India Engineering & Technology Center (BIETC) is a 5500+ engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&D, innovation, and high-quality engineering work in global markets, and leverage new-age technologies such as AI/ML, IIoT, Cloud, Model-Based Engineering, and Additive Manufacturing, shaping the future of aerospace. People-driven culture At Boeing, we believe creativity and innovation thrives when every employee is trusted, empowered, and has the flexibility to choose, grow, learn, and explore. We offer variable arrangements depending upon business and customer needs, and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration, frequent team engagements, and face-to-face meetings bring Inclusive perspectives and thoughts – enabling every voice to be heard and every perspective to be respected. No matter where or how our teammates work, we are committed to positively shaping people’s careers and being thoughtful about employee wellbeing. At Boeing, we are inclusive and transformative. With us, you can create and contribute to what matters most in your career, community, country, and world. Join us in powering the progress of global aerospace. Boeing India Engineering has an immediate opening for an Engineering Manager - Digital Circuits who will be responsible for development and management of engineers in India to perform engineering work-statements for Boeing product life cycle management. This position will work collaboratively with teams from across the globe in an integrated design environment to help deliver an engineering statement of work. The selected individual will develop and handle Engineers, interact with the program leaders from across the globe, with a vision to grow ownership in execution with their team. This position will be in Bengaluru, India , and will be reporting directly to the Sr. Electronic Manager, India. Primary Responsibilities: Manage employees performing engineering and technical activities in the areas of ASIC/FPGA verification and design. Develops and executes integrated departmental plans, policies and procedures and provides input on departmental business and technical strategies, goals, objectives. Acquires resources for department activities, provides technical management of suppliers and leads process improvements. Develops and maintains relationships and partnerships with customers, stakeholders, peers, partners and direct reports. Provides oversight and approval of technical approaches, products and processes. Provides project/Activity planning, and key milestone tracking. Manages post silicon debug support activities for validation, SW development and Test Team. Manages directly (including people reporting) the RTL, DV and DFT primarily. Integrated PD and Emulation activities Understand complex protocols and create implementable objectives for team, Protocols would include PCIe, ARINC, MIL 1553, USB, I2C and other proprietary protocols related to space and flight systems Manages, develops and motivates employees along with functional capability planning. Build capability and capacity upon SV & UVM. Nurture directed test case scenarios using VHDL and similar platforms. Should have strong verbal and written communication skills. Basic Qualifications (Required skills/experience): Bachelor’s degree or higher is required At least 12 years of experience in Digital IC design and verification, involved in at least 3 Chip Tape outs or equivalents. Proficient in tools such as Vmanager and similar tools with other EDA vendors to track and maintain verification workflow metrics for the team. Proficient in concepts such as cross domain clock sync, polymorphism. Proficient in validating the verification workflow with available limitations on tools and resources to provide maximum functional coverage on priority. Demonstrated success leading development efforts, including project management and earned value tracking. Preferred Qualifications (Desired skills/experience): Experience leading or managing in an engineering organization. Familiarity with FAA DO-254 certification. Familiar with Emulation and Safety Flow Analysis Familiar in Formal Verification techniques Familiar in Design Concepts US Person as defined by 22 C.F.R 120.15 is advantageous. Familiar with LOR verification based VCRM structure Typical Education & Experience: Education/experience typically acquired through advanced education (e.g. Bachelor) and typically 13 to 16 years' related work experience or an equivalent combination of education and experience (e.g. Master+12 years of related work experience etc.) Applications for this position will be accepted until Sept. 20, 2025 Export Control Requirements: This is not an Export Control position. Education Bachelor's Degree or Equivalent Required Relocation This position offers relocation based on candidate eligibility. Visa Sponsorship Employer will not sponsor applicants for employment visa status. Shift Not a Shift Worker (India) Equal Opportunity Employer: We are an equal opportunity employer. We do not accept unlawful discrimination in our recruitment or employment practices on any grounds including but not limited to; race, color, ethnicity, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military and veteran status, or other characteristics covered by applicable law. We have teams in more than 65 countries, and each person plays a role in helping us become one of the world’s most innovative, diverse and inclusive companies. We are proud members of the Valuable 500 and welcome applications from candidates with disabilities. Applicants are encouraged to share with our recruitment team any accommodations required during the recruitment process. Accommodations may include but are not limited to: conducting interviews in accessible locations that accommodate mobility needs, encouraging candidates to bring and use any existing assistive technology such as screen readers and offering flexible interview formats such as virtual or phone interviews.

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74922 Description Responsibilities Work with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level. Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development. Required Experience And Skills 8+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant industry experience Expertise in developing testbenches using System Verilog and UVM Experience using directed and constrained-random test methodologies, coverage closure and gate-level simulations Strong object-oriented programming knowledge using SystemVerilog Strong problem-solving and debug skills capable of isolating problems to the block level Expertise in developing test plans, implementing coverage models, and analyzing results Experience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc) Familiarity with C-code/embedded firmware/debuggers Ability to work in a dynamic environment with changing needs and requirements Ideally You Are Also Experienced In Using Formal verification methods and tools like Jasper Gold. Real-time data processing systems Audio signal processing Audio performance concepts (SNR, THD, SINAD, DR, etc.) Familiarity with standard interfaces (SPI, I2S, PDM, PWM, USB, etc.) Familiarity with wireless protocols (Wi-Fi, BLE, BT, MAC/PHY) Familiarity with wireless different processors (ARM, HiFi, RISC-V) FPGA hardware emulation Desired Experience And Skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

Technical Specialist - Design Verification Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore, Pune, Noida Location: Bangalore, Noida, Pune. Experience: 8–14 Years. About the Role: We are looking for an experienced and passionate Senior Design Verification Engineer to join our team in Bangalore, Pune, Noida. The ideal candidate will have a strong background in pre-silicon verification of complex IPs or SoCs and be capable of leading verification efforts across multiple projects. Key Responsibilities: Lead and contribute to the verification of complex IP blocks or SoC subsystems. Develop test plans, verification strategies, and coverage metrics based on design specifications. Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM. Collaborate with architects, designers, and other verification engineers to identify and debug design issues. Develop and maintain verification infrastructure, scripts, and regression systems. Perform functional and code coverage analysis, driving closure. Provide technical guidance and mentorship to junior team members. Participate in silicon bring-up and post-silicon validation when needed. Required Skills and Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. 8–14 years of hands-on experience in ASIC/SoC verification. Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa). Solid understanding of verification methodologies, functional coverage, and assertion-based verification. Experience in developing and maintaining testbenches from scratch. Strong debugging skills and familiarity with waveform viewers like Verdi or DVE. Good knowledge of scripting languages (Python, Perl, or TCL) for automation. Familiarity with version control and CI/CD systems. Preferred Qualifications: Experience in formal verification or emulation is a plus. Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB). Prior experience in leading a verification team or acting as a verification lead. Exposure to post-silicon bring-up and validation. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Technical Specialist - Design Verification Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore, Pune, Noida Location: Bangalore, Noida, Pune. Experience: 8–14 Years. About the Role: We are looking for an experienced and passionate Senior Design Verification Engineer to join our team in Bangalore, Pune, Noida. The ideal candidate will have a strong background in pre-silicon verification of complex IPs or SoCs and be capable of leading verification efforts across multiple projects. Key Responsibilities: Lead and contribute to the verification of complex IP blocks or SoC subsystems. Develop test plans, verification strategies, and coverage metrics based on design specifications. Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM. Collaborate with architects, designers, and other verification engineers to identify and debug design issues. Develop and maintain verification infrastructure, scripts, and regression systems. Perform functional and code coverage analysis, driving closure. Provide technical guidance and mentorship to junior team members. Participate in silicon bring-up and post-silicon validation when needed. Required Skills and Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. 8–14 years of hands-on experience in ASIC/SoC verification. Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa). Solid understanding of verification methodologies, functional coverage, and assertion-based verification. Experience in developing and maintaining testbenches from scratch. Strong debugging skills and familiarity with waveform viewers like Verdi or DVE. Good knowledge of scripting languages (Python, Perl, or TCL) for automation. Familiarity with version control and CI/CD systems. Preferred Qualifications: Experience in formal verification or emulation is a plus. Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB). Prior experience in leading a verification team or acting as a verification lead. Exposure to post-silicon bring-up and validation. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Technical Specialist - Design Verification Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore, Pune, Noida Location: Bangalore, Noida, Pune. Experience: 8–14 Years. About the Role: We are looking for an experienced and passionate Senior Design Verification Engineer to join our team in Bangalore, Pune, Noida. The ideal candidate will have a strong background in pre-silicon verification of complex IPs or SoCs and be capable of leading verification efforts across multiple projects. Key Responsibilities: Lead and contribute to the verification of complex IP blocks or SoC subsystems. Develop test plans, verification strategies, and coverage metrics based on design specifications. Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM. Collaborate with architects, designers, and other verification engineers to identify and debug design issues. Develop and maintain verification infrastructure, scripts, and regression systems. Perform functional and code coverage analysis, driving closure. Provide technical guidance and mentorship to junior team members. Participate in silicon bring-up and post-silicon validation when needed. Required Skills and Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. 8–14 years of hands-on experience in ASIC/SoC verification. Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa). Solid understanding of verification methodologies, functional coverage, and assertion-based verification. Experience in developing and maintaining testbenches from scratch. Strong debugging skills and familiarity with waveform viewers like Verdi or DVE. Good knowledge of scripting languages (Python, Perl, or TCL) for automation. Familiarity with version control and CI/CD systems. Preferred Qualifications: Experience in formal verification or emulation is a plus. Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB). Prior experience in leading a verification team or acting as a verification lead. Exposure to post-silicon bring-up and validation. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled engineer with 6-10 years of experience, passionate about developing cutting-edge emulation solutions for industry-standard protocols such as PCIe, CXL, and UCIe. You possess a strong background in software development using C/C++ and synthesizable RTL development with Verilog. Your deep understanding of digital design concepts, HDL languages, and scripting languages like Python or Perl will be invaluable in this role. You thrive in collaborative environments, have excellent communication skills, and are adept at solving complex problems. Your ability to interact with customers during deployment and debug processes will ensure successful implementation and satisfaction. A B.E/B.Tech/M.Tech in Electronic & Communication or Computer Science Engineering is essential. Knowledge of ARM architecture, UVM, and functional verification, along with experience in emulation, will be a significant advantage. What You’ll Be Doing: Developing emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers. Engaging in software development using C/C++ and synthesizable RTL development with Verilog. Verifying solutions to ensure high performance and reliability. Interacting with customers during the deployment and debug phases to ensure smooth implementation. Collaborating with cross-functional teams to integrate emulation solutions. Maintaining and enhancing existing emulation solutions to meet evolving industry standards. The Impact You Will Have: Driving the development of advanced emulation solutions that meet industry standards. Enhancing the performance and reliability of semiconductor products through innovative solutions. Ensuring customer satisfaction by providing robust and efficient deployment support. Contributing to the continuous improvement of Synopsys' emulation technologies. Supporting the adoption of new protocols and standards in the semiconductor industry. Strengthening Synopsys' position as a leader in chip design and verification solutions. What You’ll Need: 5+ years of relevant experience In-depth knowledge of PCIe, CXL, and UCIe protocols. Proficiency in C/C++ programming and object-oriented programming concepts. Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog. Experience with scripting languages like Python, Perl, or TCL. Familiarity with ARM architecture and UVM/functional verification is a plus. Who You Are: A collaborative team player with excellent communication skills. A problem-solver with a keen eye for detail and a passion for innovation. Adaptable and able to work effectively in a fast-paced, dynamic environment. Customer-focused, with the ability to handle deployment and debugging challenges efficiently. Committed to continuous learning and staying updated with industry advancements. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on developing and enhancing emulation solutions for cutting-edge semiconductor technologies. Our team collaborates closely with various departments to ensure the highest quality and performance of our products, driving innovation and excellence in the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Sr Design Verification Engineers to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond #SCHIEINDIA Responsibilities The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner. Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools Develop tests using UVM or C/C++ Analyse and debug test failures with designers to deliver functionally correct design. Identify and write functional coverage for stimulus and corner cases. Close coverage to plug verification holes and meet tape out requirements. Qualifications 8 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. Solid understanding of computer architecture Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments Scripting language such as Python or Perl Desirable Hands on experience in Formal property verification knowledge in high-speed protocols like DDR, PCIe, Ethernet Processor based testbenches and emulation Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Job Overview Experience: 3 – 15 years Responsibilities Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks—defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills And Experience Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies – UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

About Celestial AI As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies. This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers. ABOUT THE ROLE Celestial AI is looking for a highly motivated and detail-oriented Software Quality Assurance (SQA) Engineer to join our team. As an SQA Engineer, you will play a critical role in ensuring the quality of our software products. You will be responsible for designing, developing, and executing test plans and test cases, identifying and reporting defects, and working closely with developers to ensure that our software meets the highest standards. ESSENTIAL DUTIES AND RESPONSIBILITIES Test Case Design & Execution: Design, document, and execute detailed test cases for firmware components, drivers, communication protocols, and system-level interactions with hardware. Hardware-Firmware Integration Testing: Lead and perform testing at the hardware-firmware interface, ensuring seamless and correct interaction between embedded software and physical components (e.g., sensors, actuators, external memory, peripherals like SPI, I2C, UART). Automation Development: Design, develop, and maintain automated test scripts and test harnesses using scripting languages (e.g., Python, Bash) and specialized tools to enhance test coverage and efficiency, particularly for regression testing. Defect Management: Identify, document, track, and verify resolution of software defects using bug tracking systems. Provide clear and concise bug reports with steps to reproduce and relevant logs. Root Cause Analysis: Collaborate with firmware developers to perform in-depth root cause analysis of defects, often involving debugging on embedded targets using JTAG/SWD, oscilloscopes, logic analyzers, and other hardware debugging tools. Performance & Resource Analysis: Monitor and analyze firmware performance metrics (CPU usage, memory footprint, power consumption, boot time, latency) and validate against specified requirements. Regression & Release Qualification: Own the regression testing process and contribute significantly to the final release qualification of firmware builds. Process Improvement: Champion and contribute to the continuous improvement of firmware development and quality assurance processes, methodologies, and best practices. QUALIFICATIONS Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. 5 years of experience in Software Quality Assurance, with a minimum of 2 years directly focused on firmware or embedded software testing . Strong understanding of embedded systems concepts , including microcontrollers/microprocessors, real-time operating systems (RTOS), interrupts, memory management, and common peripheral interfaces (GPIO, I2C, SPI, UART, ADC, DAC, Timers). Proficiency in C/C++ for embedded development, with the ability to read, understand, and debug firmware code. Experience with scripting languages for test automation (e.g., Python, Bash). Hands-on experience with hardware debugging tools such as JTAG/SWD debuggers, oscilloscopes, logic analyzers, and multimeters. Familiarity with version control systems (e.g., Git) and bug tracking tools (e.g., Jira, Azure DevOps). Experience with test management tools (e.g., TestRail, Zephyr). Excellent problem-solving skills, with a methodical and analytical approach to identifying and isolating defects. PREFERRED QUALIFICATIONS Experience with continuous integration/continuous deployment (CI/CD) pipelines for embedded systems. Knowledge of networking protocols (TCP/IP) Experience with Hardware-in-the-Loop (HIL) testing, simulation, or emulation environments. LOCATION : Hyderabad, India or Singapore We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing. Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer. #LI-Onsite

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Computing & Graphics (CG) SoC Architecture team, this SoC Power Management Design Engineer will develop and design custom silicon for gaming consoles, datacenter, client, or embedded computer vision SOCs and related platforms. In this role, you will work with the lead SoC architect to define customer-specific architectures and contribute to product specifications, micro-architecture specifications, performance and power trade-offs. The role will work from early concept development through the development phases to final production. THE PERSON: In this role, you will collaborate with a network of expert architects and designers around the world where collaboration and communication skills are critical to the success of this role, and excellent organization skills are essential. You will approach sophisticated problems with a firm methodology and problem-solving technique and conduct experiments and analysis to formulate recommendations and next steps for other colleagues and SOC and IP design teams located in across multiple time zones and geographies. You will formally present your findings to co-workers, teams, and customer engineering teams. K EY RESPONSIBLITIES : Drive the physical design, and power architecture based on customer-specific requirements Work with AMD’s Engineering teams, and IP teams to help aid in their integration, implementation, and optimization of the designs through end-to-end documentation of flows etc., Ability to understand power consumption and power delivery using combination of static, dynamic models, and emulation data Analyze performance across voltages for DVFS states of IPs, including inference engines, CPUs, Graphics, memory controllers, peripheral interfaces, caches and network-on-chip fabric Interacting with the technology teams, silicon validation, and product engineering teams to establish voltage-frequency design points Working with the systems and architecture team to evaluate and define definitions for on-die PDN, power gating, package, and system power delivery Analyze effects of control algorithms for management throttling mechanisms to achieve peak performance within thermal and peak current limits P REFERRED EXPERIENCE : Solid understanding of SoC construction including fabric connectivity, memory systems, power delivery, clock distribution, floor planning, and packaging Strong understanding of SoC power management, power dissipation and mobile battery life Skills in scripting, data analysis, experience with EDA tools, physical design tools for power optimization, VLSI design flow and CMOS technology Ability to understand and model thermal control loops and throttling mechanisms Strong problem solving, organizational and communication skills, and ability to work in a dynamic and diverse environment Proficiency in scripting languages (Python) is highly preferred Experience with Power Architect, Power Artist and VisualSim a plus Detailed thinking skills. Ability deal with novel problems from different perspectives and from different levels of abstraction Ability to analyze and understand sophisticated workflows and processes, and develop innovative ways in streamlining and automating ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PM2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

🚀 We’re Hiring – Simulation Engineer (6–10 Years Experience) 🚀 Veevx, a leading product-based company in Gandhinagar, Gujarat , is looking for an experienced Simulation Engineer to join our growing team. Key Responsibilities: Develop simulation models for SoC and ASIC designs (functional validation, timing, and cycle-accurate modeling). Develop architectural high level simulation models for design space tradeoffs, including performance modeling and estimation. Work with RTL engineers to convert architectural simulation into detail RTL design. Work with Verification Team on test plan development to achieve high code coverage and functional coverage. Incorporate software code emulation to validate simulation models. Skills: Languages: C/C++, Verilog, Python Design verification ASIC design flow/tools Functional coverage Experience/knowledge: Knowledge in advanced nodes, low power SoCs, internal & external IP integration and high performance RISC-V are essential. Register-transfer-level (RTL), digital logic design, logic synthesis, clock trees optimization, timing closure, test bench development, circuit analysis, floor-planning, physical layout, and design for test (DFT), prototype bring-up, debug and validation. Knowledge on synthesis, timing analysis and formal verification. Track record of 'first-pass success' in ASIC development. Hands-on experience in Verilog, System Verilog, UVM, C/C++, Python based verification. Experience in Cluster and SoC level verification using Hybrid Simulation and Emulation based methodologies. Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments. Experience using analytical skills to craft novel solutions to tackle industry-level complex designs. Demonstrated experience with effective collaboration with cross functional teams. Preferred Qualifications: 6-10 years of experience in development of simulation, modeling and acceleration frameworks. Experience in performance verification of complex compute blocks like CPU, GPU or Hardware Accelerators, Ethernet, PCIe, DDR, HBM etc. Experience in verification of AI acceleration design. Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification. Experience with verification of ARM/RISC-V based sub-systems or SoCs. 📍 Location: Gandhinagar, Gujarat 👉 Apply now / Reach out directly via DM or email at: vpatel@veevx.com #Hiring #SimulationEngineer #ASIC #SoC #RISC-V #CareerOpportunity #Veevx

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER (ASIC - SoC Design Verification Lead) The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Senior Verification Engineer Bangalore, Karnataka, India Date posted Sep 12, 2025 Job number 1876587 Work site 3 days / week in-office Travel 0-25 % Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Sr D esign V erification E ngineers to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond #SCHIEINDIA Qualifications 8 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. Solid understanding of computer architecture Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments Scripting language such as Python or Perl Desirable: Hands on experience in Formal property verification knowledge in high-speed protocols like DDR, PCIe, Ethernet Processor based testbenches and emulation Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Responsibilities The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner. Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools Develop tests using UVM or C/C++ Analyse and debug test failures with designers to deliver functionally correct design. Identify and write functional coverage for stimulus and corner cases. Close coverage to plug verification holes and meet tape out requirements. Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

As a Portable Stimulus (PSS) Verification Lead at Vayavya Labs, you will play a crucial role in understanding customer requirements on system-level verification scenarios and developing test scenarios in PSS language and C or SystemVerilog/UVM. Your responsibilities will include executing test scenarios in pre-silicon and post-silicon environments, as well as debugging the test scenarios. Key Responsibilities: - Understand customer requirements on system-level verification scenarios - Develop test scenarios in PSS language and in C or SystemVerilog/UVM - Execute test scenarios in pre-silicon (simulation, emulation) and post-silicon environments - Debug test scenarios Qualifications Required: - Hands-on experience in C programming for embedded systems - Expertise in pre-silicon validation of system-level scenarios - Experience with verification of controllers for protocols like PCIe, Ethernet, MIPI CSI/DSI - Familiarity with verification on emulator environments Vayavya Labs has been actively contributing to the development and adoption of the PSS standard, making it a leader in the industry. By joining our team, you will have the opportunity to work on Portable Stimulus technologies and develop scenarios for various SoC sub-systems. Additionally, you will receive training on PSS as part of the ramp-up phase. You will also be involved in project planning, effort estimation, technical leadership, and mentoring other team members on PSS. It is essential to have strong analytical and problem-solving skills, excellent communication skills, and a self-managed approach to work. This position offers a great learning opportunity for engineers with experience in system-level verification scenarios and a keen interest in SoC verification technologies. Vayavya Labs is at the forefront of the industry, driving discussions and advancements in Portable Stimulus technologies. If you are eager to take on new challenges and work with cutting-edge verification methodologies, this role is perfect for you.,

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description The selected candidate will be responsible for RTL Design and Verification & Integration, collaborating closely with Architects and the Verification team. Ensuring the required design quality through Lint and CDC checks and following release checklists. Skillset/Requirements BTech/ MTech in Engineering with 2-5 years of practical experience in RTL Design. OR Equivalent Profound understanding of the end-to-end Digital design flow. Proficiency in Verilog/System-Verilog RTL logic design, debugging, and providing functional verification support. Knowledge of managing multiple asynchronous clock domains and their crossings. Familiarity with Lint checks and error resolution. Hands-on experience with APB and AXI protocols. Experience in micro-controller based designs and associated logic is advantageous. Additional experience in Digital microarchitecture definition and documentation is a plus. Exposure to synthesis timing constraints, static timing analysis, and constraint development is beneficial. Familiarity with FPGA and/or emulation platforms is advantageous. Strong communication skills, self-motivation, and organizational abilities are essential. We’re doing work that matters. Help us solve what others can’t.

🚀 We at Scaledge Technology Hiring: VLSI Verification Engineer (PCIe & CXL Expertise) 🚀 Are you a passionate verification engineer with deep expertise in PCIe and CXL protocols? Ready to work on cutting-edge semiconductor technologies? We’re looking for a VLSI Verification Engineer with 5+ years of experience to join our high-impact team! 🔧 Role Responsibilities: *) Develop and execute verification plans for high-speed interface IPs (PCIe/CXL) *) Work with SystemVerilog, UVM, and industry-standard simulation tools Collaborate with architecture and design teams to ensure functional correctness *) Debug and resolve complex issues in simulation and emulation environments 🎯 What You Bring: *) Strong hands-on experience in protocol-level verification of PCIe and/or CXL *) Proficiency in SystemVerilog, UVM, and scripting languages *) Familiarity with assertion-based verification, coverage analysis, and debug tools *) Excellent problem-solving and communication skills 📍 Location: Pune 📧 Apply Now: nupur.dodake@scaledge.io

Job Title: SOC Lead/Manager – Cyber Monitoring & Response Job Description We are seeking a highly skilled SOC Lead to oversee our Cyber Defence Operation Centre(CDOC), drive threat detection, and orchestrate incident response. This role demands deep technical expertise, strong leadership, and the ability to design and implement advanced security monitoring and response strategies. The SOC Lead will be responsible for real-time monitoring, threat intelligence analysis, forensic investigations, and security automation, ensuring that the organization remains resilient against evolving cyber threats. Location: [Gurgaon] Job Type: Full-time | On-site/Hybrid Reports To: Associate Director of Cyber Defence Operation Centre Key Responsibilities: SOC Operations & Security Monitoring Lead and manage the 24/7 Security Operations Center (SOC), ensuring continuous threat detection and response. Working extensively on SIEM (XSIAM. Arcsight, Splunk, QRadar, ELK, Sentinel, etc.) and other security monitoring tools. Oversee 24/7 monitoring of security events and alerts. Ensure effective use of SIEM (Security Information and Event Management) tools. Prioritize, analyze, and manage security incidents. Improve threat intelligence capabilities and integrate with threat intelligence feeds.Continuously optimize detection rules, correlation logic, and security alerts to minimize false positives and improve response times. Incident Response & Management Develop and enforce incident response plans (IRPs). Ensure timely response to cyber threats, minimizing impact. Coordinate with stakeholders during major incidents. Conduct post-incident analysis and lessons learned exercises. EDR/XDR (Endpoint Detection & Response / Extended Detection & Response) CrowdStrike Falcon – AI-powered threat detection with real-time response. Palo Alto XDR – Extended Detection and Response. Microsoft Defender for Endpoint – Integrated with Azure security solutions. – Behavioral AI-driven endpoint protection. Carbon Black (VMware) – Next-gen EDR with cloud analytics. Sophos Intercept X – Machine-learning-based ransomware prevention. Threat Intelligence Platforms (TIP) Recorded Future – AI-driven threat intelligence analysis. MISP (Malware Information Sharing Platform) – Open-source threat sharing platform. Flashpoint Threat Intel Outseer AFCC ( Previously RSA) IBM X-Force Exchange – Intelligence-sharing with global threat data. Anomali ThreatStream – Automated threat intelligence processing. VirusTotal Enterprise – File and URL malware scanning with shared intelligence. Compliance & Reporting Ensure compliance with security frameworks (ISO 27001, NIST, GDPR, etc.). Maintain accurate security logs and reports for audits. Prepare executive-level reports on security incidents and risk posture. Red Team Collaboration & Penetration Testing Support Coordinate with Red Teams & Ethical Hackers to improve blue team defenses and detection coverage. Assist in purple teaming exercises to fine-tune SOC detection capabilities against adversarial TTPs. Leverage adversary emulation tools (Caldera, Atomic Red Team, MITRE CALDERA) to validate detection logic. Collaboration & Communication Act as a key liaison between IT, legal, compliance, and business units. Coordinate with external security teams, vendors, and law enforcement. Conduct security awareness training for employees. Leadership & Team Development Lead and mentor a team of SOC analysts (L1-L3), threat hunters, and DFIR specialists. Foster a culture of continuous learning, conduct CTF challenges, and ensure team certifications. Define KPIs & metrics to measure SOC effectiveness (MTTD, MTTR, False Positive Rates, etc.). Define SOC objectives, goals, and security strategies. Align SOC operations with business and IT security objectives. Lead, mentor, and train SOC analysts and security engineers. Develop and maintain SOC policies, procedures, and playbooks. Required Technical Skills & Experience: Experience: 7+ years in cybersecurity, with at least 3 years in a SOC leadership role. SIEM & Log Analytics: XSIAM, ArcSight, Splunk, Elastic Stack (ELK), QRadar, Microsoft Sentinel Threat Intelligence: MITRE ATT&CK, Cyber Kill Chain, MISP, STIX/TAXII. Incident Response & Forensics: Volatility, Wireshark, FTK, EnCase, Sleuth Kit, YARA. Endpoint Security & EDR/XDR: CrowdStrike Falcon, Microsoft Defender, Palo Alto XDR, SentinelOne, Carbon Black. Cloud Security: AWS GuardDuty, Azure Security Center, Google Chronicle, CSPM, CNAPP. Compliance & Risk: NIST 800-53, ISO 27001, PCI-DSS, SOC2, GDPR, CIS Benchmarks. Location: IND Gurgaon - Bld 14 IT SEZ Unit 1, 5th, 6th and 17th Flr Language Requirements: Time Type: Full time If you are a California resident, by submitting your information, you acknowledge that you have read and have access to the Job Applicant Privacy Notice for California Residents R1653048

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description The selected candidate will be responsible for RTL Design & Integration, collaborating closely with Architects and the Verification team. Ensuring the required design quality through Lint and CDC checks and following release checklists. Skillset/Requirements BTech/ MTech in Engineering with 1-3 years of practical experience in RTL Design. Profound understanding of the end-to-end Digital design flow. Proficiency in Verilog/System-Verilog RTL logic design, debugging, and providing functional verification support. Knowledge of managing multiple asynchronous clock domains and their crossings. Familiarity with Lint checks and error resolution. Hands-on experience with APB and AXI protocols. Experience in micro-controller based designs and associated logic is advantageous. Additional experience in Digital microarchitecture definition and documentation is a plus. Exposure to synthesis timing constraints, static timing analysis, and constraint development is beneficial. Familiarity with FPGA and/or emulation platforms is advantageous. Strong communication skills, self-motivation, and organizational abilities are essential. We’re doing work that matters. Help us solve what others can’t.

We are looking for more than 5years of experience. Job Description for DV You will be part of the team verifying IPs and SoCs leading to first Si success. Manage and lead a team of Verification engineers IP verification is coverage driven using latest industry standard methodologies and HVLs. Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases. Code coverage, Functional coverage and assertions are desired. ARM based SoC verification experience is an added advantage. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus. Multiple positions with emphasis on AMS and Power aware verification. Should have worked on GLS. Key Responsibilities: Lead Verification Efforts: Manage and mentor a team of IP and SoC verification engineers. Drive verification strategy to ensure first silicon success. Verification Planning & Execution: Define test plans and verification methodologies using UVM/OVM. Develop and maintain reusable testbenches and test cases. Coverage & Quality Assurance: Ensure high-quality verification through code coverage, functional coverage, and assertions. Perform Gate-Level Simulations (GLS) and Low Power Verification. Collaboration & Communication: Work closely with design, architecture, and validation teams. Provide regular updates and technical guidance to stakeholders. Tool & Script Development: Automate verification tasks using scripting languages like Python, Perl, Shell, and Tcl. Utilize industry-standard tools for emulation, LEC, and AMS verification. Primary Skills: Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting – Perl, Python, Shell, and Tcl. Secondary Skills: Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR. Education Qualification: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field