MTS Software Development Eng. Hyderabad, India Engineering 58385 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS Product Engineer The Product Engineer position is in the Customer Enablement and Success group, located in Hyderabad, Telangana, India, for an experienced application engineer to focus on FPGA & ACAP design methodologies, compilation flows, design closure ease-of-use, tools specification, validation, documentation and key customers support. As a member of a highly seasoned Product Development Engineering team, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve the user experience and productivity and enable the next generation of high performance computing designs across the UltraScale and Versal ACAP device families. Daily activities will include the following duties: Own a Vivado product area and become the future team champion to work on high impact projects and with key customers. Drive critical customer escalations to closure and contribute to new technologies rollout. Contribute to triaging reported issues in several Vivado product areas, such as design entry, NoC and IP design flows, compilation, and help engineering address them effectively. Actively explore innovative methodologies and their impact on flow and design practices for the new 7nm Versal ACAP family. Work closely with AMD Business Units (Data Center, Wired, Wireless, Emulation & Prototyping, Test Equipment) to improve their designs, products and customer experience. Develop and deliver training materials on new features and methodologies. Stay current with and propose the internal use of industry approaches, algorithms, and practices Education and Experience Requirements MS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 8 years of relevant experience. Customer Awareness: Has excellent working knowledge of RTL-based design flows and expectations. Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with intermediate-to-advanced understanding in timing analysis and closure. Scripting experience (Tcl, Perl, Python) is desired. Design Enablement: Has good understanding of design methodologies for system design, AXI protocol, network-on-chip, design closure. Problem Solving: Ability to handle and solve complex system level issues. Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear. Can report out to management in a concise and actionable manner. Teamwork : Able to work with several teams across sites and domains with a positive attitude under variable workloads. #LI-MK1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Soc Design Architect Hyderabad, India Engineering 64362 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Soc Design Architect THE ROLE: We are seeking a seasoned SoC Design Lead with expertise or significant interest in leading the development of High end networking silicon. You have had significant success driving the execution of SoCs working with IP, Subsystem, Physical design teams. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead for driving bleeding edge networking IP and silicon driving milestones across multiple geographies. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at distilling the SOC design challenges driving respective teams to adhere to milestones, leveraging you technical expertise in solving SoC design issues and are proactive in communicating progress to upper management KEY RESPONSIBILITIES: Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements Knowledge sharing and other contributions to Platform & System Architecture As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or Networking, Memory sub-system, Fabrics, Switches, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security Experience analyzing CPU, Networking or System-level Micro-Architectural features to identify performance bottlenecks within different workloads Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in related discipline preferred #LI-PS1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Software Verification Engineer Hyderabad, India Engineering 57588 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The primary responsibility is the validation of BootROM, which includes the following tasks: Develop and execute test cases to validate all boot peripherals from where the FSBL (First Stage Boot Loader) is copied. Example: xSPI, SD, eMMC, UFS, USB Create and execute test cases to validate all proprietary boot sequences. Develop and execute test cases to validate all internal boot modes. Write and run test cases to validate all supported authentication algorithms. Develop and execute test cases to validate all supported encryption/decryption algorithms. Automate tests using Python. Perform testing on prototyping/emulation platforms, including X86 emulation. Identify, document, and track issues using JIRA. Report coverage metrics using tools such as Verdi and add tests to ensure maximum source line coverage. Review requirements and create associated test cases to ensure traceability. Collaborate with different teams to resolve any blockers. Engage in constructive discussions with the design team to improve the quality of the BootROM. Conduct security threat analysis using internal tools. Adhere to safety processes while performing the above tasks. #LI-SK4 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SoC Design Verification Lead New Dehli, India Engineering 64584 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER (ASIC - SoC Design Verification Lead) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. #LI-RP1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

ASIC SoC Design Verification New Dehli, India Engineering 64580 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SE NIOR SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification Engineer) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 6+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. #LI-SR4 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Experience required 8+ Years. Emulation experience on any available platforms (Palladium, Veloce or Zebu) including bring-up, VIP interfacing, build flow, debug, performance/throughput measurement Good understanding of the SOC designs and verification aspects Experience with Verilog, System Verilog, UVM, SVA Knowledge of communication/interface protocols would be a plus: PCIe, USB3/4, LPDDR5/4 , QUP, eMMC, SD, UFS Knowledge of the processor RISCV, ARM Knowledge of GLS and GLE flows would be a plus Proficient in writing scripts using any languages (Perl, TCL, bash, Python) Experience with waveform debug tools like Verdi Strong communication skills and ability to work as a team with multiple stakeholders Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 3 years of experience with multiple SoCs with Silicon success. Experience with chip design flow. Preferred qualifications: Experience in micro-architecture and coding in one or more of the following areas: memory compression, interconnects, coherence, cache. Knowledge of ARM based SoC, Debug (coresight). Understanding of cross-domain involving domain validation, design for testing, physical design, and software. Understanding of Verilog or System Verilog language. Proficiency with ASIC design methodologies for front quality checks like; Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Work on both the IP design and integration activities including: plan tasks, support, hold code and design reviews, contribute on sub-system/chip-level integration. Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for IPs. Interact with the subsystem team and plan System-on-Chip (SoC) milestones, plan quality checks as part of SoC milestones (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.). Work with cross-functional teams of verification, design for test, physical design, emulation, and software to make design decisions and represent project status throughout the development process. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Show more Show less

A Hardware-Assisted Verification Expert with deep knowledge of IP interfaces such as PCIe and DDR, and experience with Zebu, HAPS, and EP platforms. You have a proven track record in IP verification and methodology ownership focused on emulation and verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Your hands-on approach, collaborative mindset, and proactive attitude drive results. You are passionate about working closely with customer, RND, PV and Product Engineering to work on latest emulation technologies to deploy and enhance optimal solutions covering the entire ecosystem of Large SOCs, Controller and PHY, with a focus on emulation and acceleration. What You ll Be Doing: Bridging and closing gaps between the available or required Emulation hyper scaler Designs, IP and product validations of all its functions. Reporting metrics and driving improvements in Emulation PE and RND Using your expertise to drive requirements for the Emulation and ensure its correct usage and deployment in verification strategies for customers. Staying ahead of evolving standards, understanding future changes, specification errata, and driving this understanding into both the Emulation IP and Design IP teams. The Impact You Will Have: Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. Driving innovation in defining requirements for product development, in the context of Emulation. Evolving and integrating best-in-class methodologies within the organization. Standardizing and optimizing workflows to increase efficiency and compliance. What You'll Need: 8+ years of relevant experience. Results-driven mindset. Exposure to large design emulation compiles along with advanced protocols like PCIe and DDR interfaces. Experience with Zebu in the context of technology and SW validation. Proven track record in product deployment, specifically emulation. Experience in cross-functional collaborations. Excellent communication skills and a beacon for change. Adaptability and comfort in a matrixed, international environment.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Noida . But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! This is your role This role involves developing and implementing emulation test plans to validate sophisticated semiconductor products. The engineer will leverage hardware description languages such as Verilog and VHDL to design, implement, and debug emulation models. Teamwork is a key aspect of this role, as it requires close coordination with design, verification, and software teams to troubleshoot and resolve technical issues optimally. The position plays a meaningful role in ensuring the functionality, performance, and reliability of products before they reach the market. Key Responsibilities Develop and implement emulation test plans for product validation. Use HDL languages (Verilog, VHDL) to design, implement, and debug emulation models. Collaborate with design, verification, and software teams to identify and resolve issues. Requirement We are looking for candidates with Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field. We are seeking Candidates with minimum 3+ Years of Experience. We need someone who has experience with HDL languages (Verilog, VHDL) and digital design. Strong background in emulation and validation of complex digital systems. Excellent problem-solving skills and attention to detail! Show more Show less

Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification of all its functions, covering both the Controller and PHY. Reporting metrics and driving improvements in Emulation IP. Using your expertise to drive requirements for the Emulation IP and ensure its correct usage and deployment in verification strategies for both Controller and PHY. Staying ahead of evolving standards, understanding future changes, specification errata, and driving this understanding into both the Emulation IP and Design IP teams. Reviewing test plans in both Emulation IP and Design IP to ensure they deliver the required function, feature, and quality to be best in class. The Impact You Will Have: Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. Driving innovation in defining requirements for IP product development, in the context of Emulation. Evolving and integrating best-in-class methodologies within the organization. Standardizing and optimizing workflows to increase efficiency and compliance. What You'll Need: 10+ years of relevant experience. Results-driven mindset. Exposure on advanced protocols like PCIe and DDR interfaces. Experience with Zebu in the context of technology and IP verification. Proven track record in IP product development, specifically emulation. Experience in cross-functional collaborations. Excellent communication skills and a beacon for change. Adaptability and comfort in a matrixed, international environment.

MTS Software Development Eng. Hyderabad, India Engineering 58385 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS Product Engineer The Product Engineer position is in the Customer Enablement and Success group, located in Hyderabad, Telangana, India, for an experienced application engineer to focus on FPGA & ACAP design methodologies, compilation flows, design closure ease-of-use, tools specification, validation, documentation and key customers support. As a member of a highly seasoned Product Development Engineering team, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve the user experience and productivity and enable the next generation of high performance computing designs across the UltraScale and Versal ACAP device families. Daily activities will include the following duties: Own a Vivado product area and become the future team champion to work on high impact projects and with key customers. Drive critical customer escalations to closure and contribute to new technologies rollout. Contribute to triaging reported issues in several Vivado product areas, such as design entry, NoC and IP design flows, compilation, and help engineering address them effectively. Actively explore innovative methodologies and their impact on flow and design practices for the new 7nm Versal ACAP family. Work closely with AMD Business Units (Data Center, Wired, Wireless, Emulation & Prototyping, Test Equipment) to improve their designs, products and customer experience. Develop and deliver training materials on new features and methodologies. Stay current with and propose the internal use of industry approaches, algorithms, and practices Education and Experience Requirements MS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 8 years of relevant experience. Customer Awareness: Has excellent working knowledge of RTL-based design flows and expectations. Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with intermediate-to-advanced understanding in timing analysis and closure. Scripting experience (Tcl, Perl, Python) is desired. Design Enablement: Has good understanding of design methodologies for system design, AXI protocol, network-on-chip, design closure. Problem Solving: Ability to handle and solve complex system level issues. Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear. Can report out to management in a concise and actionable manner. Teamwork : Able to work with several teams across sites and domains with a positive attitude under variable workloads. #LI-MK1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience developing in C, Rust, or C++. 3 years of experience in software development for embedded systems, kernel drivers, or device drivers. 3 years of experience in testing and launching software products on embedded devices. Preferred qualifications: Experience in development with C, Rust or C++ for firmware applications. Experience in power-aware engineering practices. Experience with embedded operating systems (e.g., Linux, FreeRTOS, SafeRTOS, ZephyrOS, etc.). Experience in working with hardware register interfaces and device specifications. Experience with embedded software environments including constrained memory and code on ARM processors. About the job Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google’s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Develop firmware in C, C++, or Rust for embedded microcontrollers in System on a Chip (SoC) projects. Study hardware designs, prototype software based simulation, and engage in hardware/software co-design efforts to design and implement platform power management. Work with early hardware prototypes, emulation, software-simulation of SoC and subsystem designs to verify and enable functionality. Develop software based hardware simulations to allow early explorations of software/hardware interfaces and support early architecture decisions. Write production level firmware code, and support it through to product launch. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s CSoC DV, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and system-level verification Specifying design verification plan at soc level/IP level Specifying or reviewing verification plans for complex blocks within the ASIC Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes : o self-checking, reusable, automated verification environment : both at full-chip & block level o Constrained random generators and reference models PREFERRED EXPERIENCE: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering Minimum 8+ years of experience in ASIC Design Verification Must have excellent knowledge of ASIC Design Flow and SOC architecture Experience in developing complex testbench/model in verilog, System verilog or SystemC Experience with coverage-based verification methodology Experience in writing testplans and testcases Excellent debug skills in functional simulations are must. Experience in random test generation, coverage analysis, failure debug Strong Verilog, SystemVerilog, PLI interface, C/C++, Perl/Shell scripts programming skills. Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Must have good communication skills and the ability/desire to foster a team environment. Experience in PCIE and USB protocols verification Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We make real what matters. This is your role! Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and improve these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will cooperate with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds We seek a graduate with an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute Phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. We value sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. Knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a phenomenal teammate, resilient and candid, Enjoy learning new things and build knowledge base in new area. We’ve got quite a lot to offer. How about you? This role is based in Noida but you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the world’s most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-EDA #LI-Hybrid

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Engineer, Design Verification Responsibilities: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry Minimum Qualifications: Track record of 'first-pass success' in ASIC development cycles Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 14+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 14+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Preferred Qualifications: Experience in development of UVM based verification environments from scratch Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet Experience working across and building relationships with cross-functional design, model and emulation teams About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta. Show more Show less

Dear VLSI Talent , We are TA team of L&T technology services looking to connect with Experienced people who has ARM experience for our team in Bengluru Responsibilities : You should be a verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/PCIe/CXL, DDRx/LPDDRx integration verification in SoC RTL. Project experience with ARM based ecosystem components ( A-series ARM Cores, SMMU, GIC, Core sight, NIC and other complex bus interconnects ) Your key responsibilities will include writing test plans, defining test methodologies, developing SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, setting schedules, and quality checkpoints. Collaborate with engineers from design & performance analysis Required Skills and Experience : Proven understanding of digital hardware design and Verilog/System Verilog HDL Experienced in one or more of various verification methodologies – UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. “Nice To Have” Skills and Experience : Knowledge of SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Regards, Sreenath VIjayan team id -vlsita@LnttsGroup.onmicrosoft.com Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS Product Engineer Duties The Product Engineer position is in the Customer Enablement and Success group, located in Hyderabad, Telangana, India, for an experienced application engineer to focus on FPGA & ACAP design methodologies, compilation flows, design closure ease-of-use, tools specification, validation, documentation and key customers support. As a member of a highly seasoned Product Development Engineering team, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve the user experience and productivity and enable the next generation of high performance computing designs across the UltraScale and Versal ACAP device families. Daily activities will include the following duties: Own a Vivado product area and become the future team champion to work on high impact projects and with key customers. Drive critical customer escalations to closure and contribute to new technologies rollout. Contribute to triaging reported issues in several Vivado product areas, such as design entry, NoC and IP design flows, compilation, and help engineering address them effectively. Actively explore innovative methodologies and their impact on flow and design practices for the new 7nm Versal ACAP family. Work closely with AMD Business Units (Data Center, Wired, Wireless, Emulation & Prototyping, Test Equipment) to improve their designs, products and customer experience. Develop and deliver training materials on new features and methodologies. Stay current with and propose the internal use of industry approaches, algorithms, and practices Education And Experience Requirements MS or equivalent work experience in Electrical Engineering or similar technology area, with minimum 8 years of relevant experience. Customer Awareness: Has excellent working knowledge of RTL-based design flows and expectations. Product Knowledge: Has good working knowledge of the entire FPGA or ASIC design process and tool flow, with intermediate-to-advanced understanding in timing analysis and closure. Scripting experience (Tcl, Perl, Python) is desired. Design Enablement: Has good understanding of design methodologies for system design, AXI protocol, network-on-chip, design closure. Problem Solving: Ability to handle and solve complex system level issues. Technical Communication: Can simplify and communicate even the most complex subjects, making options, tradeoffs, and impact clear. Can report out to management in a concise and actionable manner. Teamwork: Able to work with several teams across sites and domains with a positive attitude under variable workloads. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams Preferred Experience Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Custom Compute & Storage - CCS BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell technology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect As a Senior Director, you’ll be responsible for collaborating with various teams to develop strategies, pushing the IP roadmap, and supporting multiple SOCs. This starts at the product definition phase with architecture and marketing then continues through execution of all efforts required including supporting productization. You’ll provide leadership in the development of highest value-add IP, subsystem & SoC plans and strategies with cutting edge process, speed and performance designs. The planning and execution need to be rationalized with budget and market timing requirements. Experience and judgement in determining the value of the tasks defined and executed by the team is important. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology looking for ways to improve the value and quality of the effort while keeping cost in budget. Manage and continue to build a team of complex sub-system, co-processors, accelerator and SoC engineers. The managed team includes design, verification, and collaborating with the Physical Design, DFT & Validation teams. Develop methodologies and infrastructure with evolving technology challenges including cutting edge semiconductor process, I/O’s, networking bandwidth, embedded cores, and co-processors. Work with architecture, SoCs, software, firmware, program management and post-silicon design teams for plan development and execution. Provide technical mentoring for team members. Actively engage in efforts to find improvements in methodologies, techniques, and automation Own schedules and reporting of progress metrics What We're Looking For 25 years of relevant industry experience in Semiconductor design & development Demonstrated ability to lead a multi-disciplinary team, show initiative, collaborate and communicate effectively with team members across functions & cultures. Experience in all phases of design from concept through productization. Understand & appreciate the complexity of data centers, server class or networking chipsets & prior experience with successful first silicon success. Ability to recruit and retain engineering talent. Demonstrated mentoring of junior staff. BS degree or higher in EE or CE or CS with 25+ years or more of RTL and/or verification experience 10 + years of experience managing a Design/DV/Emulation & related teams. Preferred Qualifications Experience with Full chip design, development & emulation of complex designs targeting Datacenters, Servers, Enterprise/Networking domain. Expert in developing IP, subsystem, Chiplets and SOCs Experience with one or more high-speed IO technologies: DDR, PCIe, CXL, Ethernet Management of cross-site teams Knowledge of industry standard SOC components (bus fabrics, I/O devices, processors) Knowledge of HW-SW co-development and silicon validation cycle Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

Department: Engineering Employment Type: Permanent - Full Time Location: Gurgaon - India Description The Company: At Lummus Technology, innovation thrives, and excellence is a shared pursuit. When you join the Lummus Family, you are empowered to make an impact and be part of a dynamic team that celebrates creativity, encourages professional development, and fosters collaboration. From our technology portfolio to our global workforce, Lummus is growing at a rapid pace, and we hope that you will grow with us during this exciting time. Key Responsibilities Job Responsibilities Independently lead OTS and other advanced simulation solutions Support leadership with developing proposals, estimates and product demos Develop standards and best practices for project documents like Functional Design Specifications (FDS), modeling guideline, input data collection and project schedule. Provide mentoring to enhance junior engineers’ dynamic simulation skillsets Deliver training exercises to both internal and external trainees using Lummus digital centers. Manage the project team to develop plant wide process simulation models based on Lummus proprietary process technologies. Translate, integrate, and interface with DCS and ESD control systems Participate in the testing (MAT, FAT, and SAT), acceptance and maintenance of OTS Ensure that the Scenarios and Malfunctions simulation strategies are developed in compliance with the Customer Specifications Support the testing, implementation, and start-up of the plant process control systems including FAT/SAT for verification and validation of systems Support the development of commissioning plans and startup/shutdown procedures Lead engineering study projects with multiple teams simultaneously Report project progress, risks & mitigate issues Clients (EPC/End User/Vendor/Partners) Coordination Skills, Knowledge & Expertise Qualifications Bachelors’/Masters’/Ph.D. Degree in Chemical Engineering Experience with Lummus Technology processes are preferred 15 to 20 years of post-academic experience with developing Operator Training Simulators and/or Dynamic Simulations for oil and gas, refinery and chemical processes. Experience managing multiple full cycle OTS projects (both emulation and direct-connect) as a technical lead from KOM to SAT and Training Possess in-depth knowledge about the systems, process, equipment, and controls Excellent communication and presentation skills both written and verbal Accountable and delivers on commitments in a timely manner Proven proficiency in steady state & dynamic simulation using commercial software (hands on experience with Aspen/Honeywell/Aveva preferred) Experience with Industrial Control Systems (Honeywell, Emerson, Schneider, Yokogawa, BHGE Compressor/Turbine Controller) Proven ability to interpret the actual physical problem and system controls and develop a dynamic simulation model which will represent the system response under various operating conditions Thorough understanding of P&IDs, equipment and instrument process data sheets, general arrangement drawings, development/review of process control philosophies and control narratives, and process and emergency shutdown specifications including Cause & Effect charts. With a heritage spanning more than 115 years and a focus on innovation that has resulted in more than 140 technologies and 4,100 patents, Lummus is the global leader in the development and implementation of process technologies that make modern life possible. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER (ASIC - SoC Design Verification Lead) The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Hybrid Description and Requirements "At BMC trust is not just a word - it's a way of life!" We are an award-winning, equal opportunity, culturally diverse, fun place to be. Giving back to the community drives us to be better every single day. Our work environment allows you to balance your priorities, because we know you will bring your best every day. We will champion your wins and shout them from the rooftops. Your peers will inspire, drive, support you, and make you laugh out loud! We help our customers free up time and space to become an Autonomous Digital Enterprise that conquers the opportunities ahead - and are relentless in the pursuit of innovation! The IZOT product line includes BMC’s Intelligent Z Optimization & Transformation products, which help the world’s largest companies to monitor and manage their mainframe systems. The modernization of mainframe is the beating heart of our product line, and we achieve this goal by developing products that improve the developer experience, the mainframe integration, the speed of application development, the quality of the code and the applications’ security, while reducing operational costs and risks. We acquired several companies along the way, and we continue to grow, innovate, and perfect our solutions on an ongoing basis. The IZOT product line includes BMC’s Intelligent Z Optimization & Transformation products, which help the world’s largest companies to monitor and manage their mainframe systems. The modernization of mainframe is the beating heart of our product line, and we achieve this goal by developing products that improve the developer experience, the mainframe integration, the speed of application development, the quality of the code and the applications’ security, while reducing operational costs and risks. We acquired several companies along the way, and we continue to grow, innovate, and perfect our solutions on an ongoing basis. We are seeking an experienced, strategic, and hands-on Manager - Product Security to lead a growing team of penetration testers supporting BMC’s IZOT product line. This team focuses on offensive security assessments across mainframe-based solutions and modern application ecosystems. In this leadership role, you will manage a team of skilled professionals performing deep security testing, red teaming, vulnerability analysis, and secure architecture reviews. You’ll be responsible for setting strategic goals, driving security initiatives, and ensuring secure-by-design practices are embedded across product development lifecycles. This position requires a solid blend of technical expertise in offensive security, deep understanding of mainframe and modern application architectures, and strong leadership to influence and drive results across cross-functional teams. To ensure you’re set up for success, you will bring the following skillset & experience: Bachelor's or master's degree in computer science, Information Security, or related field. 8+ years in cybersecurity roles, with 3+ years in technical leadership or management capacity. Proven experience leading or performing penetration testing on both mainframe and modern platforms. Demonstrated experience conducting red team-style assessments or advanced threat emulation on mainframe and modern systems. Proficient in tools such as: Mainframe utilities: REXX, ISPF, JCL Security tools: Nmap, Burp Suite, Wireshark, custom scripts Proficient in scripting and automation skills (Python, REXX, Bash, or similar). Experience delivering technical and executive-level security reports. Strong communication and leadership skills, with a proven ability to lead technical teams or projects. Experience producing board-level reports and presenting findings to senior stakeholders. Exposure to hybrid environments (mainframe to cloud integrations, modernization efforts). Familiarity with modern enterprise integration methods (REST, SOAP, MQ, FTP) that interface with mainframe services. CA-DNP Our commitment to you! BMC’s culture is built around its people. We have 6000+ brilliant minds working together across the globe. You won’t be known just by your employee number, but for your true authentic self. BMC lets you be YOU! If after reading the above, You’re unsure if you meet the qualifications of this role but are deeply excited about BMC and this team, we still encourage you to apply! We want to attract talents from diverse backgrounds and experience to ensure we face the world together with the best ideas! BMC is committed to equal opportunity employment regardless of race, age, sex, creed, color, religion, citizenship status, sexual orientation, gender, gender expression, gender identity, national origin, disability, marital status, pregnancy, disabled veteran or status as a protected veteran. If you need a reasonable accommodation for any part of the application and hiring process, visit the accommodation request page. < Back to search results BMC Software maintains a strict policy of not requesting any form of payment in exchange for employment opportunities, upholding a fair and ethical hiring process. At BMC we believe in pay transparency and have set the midpoint of the salary band for this role at 4,542,800 INR. Actual salaries depend on a wide range of factors that are considered in making compensation decisions, including but not limited to skill sets; experience and training, licensure, and certifications; and other business and organizational needs. The salary listed is just one component of BMC's employee compensation package. Other rewards may include a variable plan and country specific benefits. We are committed to ensuring that our employees are paid fairly and equitably, and that we are transparent about our compensation practices. ( Returnship@BMC ) Had a break in your career? No worries. This role is eligible for candidates who have taken a break in their career and want to re-enter the workforce. If your expertise matches the above job, visit to https://bmcrecruit.avature.net/returnship know more and how to apply. Min salary 3,407,100 Mid point salary 4,542,800 Max salary 5,678,500 Show more Show less

Manage an ASIC design verification team and/or managers responsible for various processing blocks in a SOC. Drive verification planning and execution, innovative verification methodology development, functional and code coverage closure. Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams Design Verification Engineering Manager Responsibilities: Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's Long Range Plan objectives Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing Build, lead, and support a team of ASIC engineers through hiring, training, and guidance to drive on-time and on-budget product delivery Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs Define, implement and maintain key performance indicators (KPI) for areas of responsibility Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors Support managers supporting design verification team Minimum Qualifications: B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience 12+ years experience in ASIC/SoC design verification 8+ years of experience as a People Manager, leading people managers and senior ICs. Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal Track record of first-pass success in ASIC Development Experience working across multiple projects and adjusting priorities in partnership with stakeholders Experience managing and delivering UVM constrained random test benches Experience with interpreting functional specs and creating comprehensive test plan Experience managing managers who are supporting small/mid size teams Preferred Qualifications: Hands-on experience with complex subsystems like memory, LPDDR, HBM, cache, PCIe, or network-on-chip including performance verification In depth knowledge of at least one of these areas - video coding standards, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework Experience in formal verification techniques and methodologies About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta. Show more Show less

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Engineer, Design Verification Responsibilities: Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the design/arch team. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality. Minimum Qualifications: Currently has, or is in the process of obtaining a Bachelor's degree in Electronics Engineering, Computer Engineering, Computer Science, VLSI, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta. Experience using constrained-random, coverage driven verification or C/C++ verification. Experience in verifying a IP block using standard DV based techniques. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments. Understanding in at least one of the following areas: computer architecture, CPU, GPU, networking, interconnects, fabrics or similar designs. Preferred Qualifications: Currently has, or is in the process of obtaining, a Master’s degree in Electronics Engineering, Computer Engineering, Computer Science or similar technical field. Experience in development of SystemVerilog/UVM based verification environments from scratch. Experience debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools. Experience in verification of any peripheral IPs like UART, SPI, I2C and exposure to protocols like APB, AXI Experience working in a CPU/GPU environment. Experience with revision control systems like Mercurial(Hg), Git or SVN. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta. Show more Show less

The Design Methodologies and Tools Engineer / Architect develops and applies Computer Aided Design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems. Assesses architecture and hardware limitations, plans technical projects in the design and development of CAD software. Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters. Develops routines and utility programs. Prepares design specifications, analysis and recommendations for presentation and approval. May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services. Key Responsibilities Provide technical leadership to define, enable, implement, automate and drive tool/flow/methodology to improve SoC integration efficiency. quality, cost and predictability. Work with architects and design team to understand and continuously improve design process from specification to tapeout. Interface with the architecture, SoC integration, power, Design implementation, Power, Design Verification and Physical design teams to identify complex technical issues/risks and optimize the implementation efficiency and cost. Support the SoC Design and Integration team on project execution. You should be familiar with SoC level Clock and Reset, low power design, UPF, CDC/RDC/LINT, DFT, top level integration of connectivity, system bus, peripherals and processor. We are looking for someone who is technically hands on and a great team player. Preferred Experience Bachelor’s or Master’s degree in related discipline with 15+ years' experience preferred. Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: SoC integration, Frontend-design, Design Verification, Design Emulation, System/performance/power modeling, Design handoffs, Design management, Design reuse, CAD/Automation algorithms. Experience analyzing Design and Verification methodologies/flows to identify bottlenecks, left-shift opportunities, and Demonstrated tools/flows/methodologies/automation expertise in SoC integration, Verification, Emulation, low power design, power optimization, Functional Safety, System modeling, Synthesis and anlysis. Experience with scripting in Perl, Python, TCL, and C/C++. Excellent communication and problem solving skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies. The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles. Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is: $202,900 to $279,000 annually More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. Show more Show less