Key Responsibilities Develop, integrate, and debug embedded software using C/C++ on custom SoC platforms. Validate multi-IP SoC designs including controller-level and protocol-level validation. Work closely with hardware and software teams to ensure robust hardware/software integration. Perform hands-on lab bring-up and debug using tools like oscilloscopes, logic analyzers, JTAG, Lauterbach, etc. Script automation and regression suites for validation using Python, Shell, or Perl. Work on system-level performance tuning, profiling, and optimization. Understand and implement protocols like AMBA (AXI, AHB, APB), USB, PCIe, and NVMe. Participate in board bring-up, driver development, and integration testing. Required Skills & Experience Bachelors degree in Electronics, Computer Science, or related field. 5+ years of industry experience in embedded systems and/or SoC validation. Proficiency in C/C++ and scripting (Python/Shell/Perl). Solid understanding of AMBA bus protocols AXI, AHB, APB. Experience in SoC validation with multi-IP environments and protocol-level testing. Strong debugging skills and hands-on experience with lab tools. Experience with RTOS, bootloaders, Linux device drivers, and hardware abstraction layers. Good knowledge of ARM architecture and modern memory subsystems. Preferred Qualifications Exposure to security protocols and controller validation (e.g., UFS, NVMe, USB). Familiarity with emulators, waveform-based debug environments. Experience with performance analysis and system-level optimization. Exposure to DRAM validation, system BIOS, and ARM/x86 assembly.
Roles & Responsibilities: Be part of a team to verify or emulate/prototype complex system on a chip designs. Interact with design engineers to identify important verification scenarios. RTL Design / porting of ASIC RTL targeting FPGA prototyping and emulation platforms, such as Synopsys ZEBU, Cadence Palladium or Siemens Veloce Synthesis, PNR and timing analysis of RTL on industry standard prototyping and emulation platforms Qualification, Experience & Skills desired: Bachelor's degree in Electrical/Electronics Engineering with 5+ years of relevant experience, or masters degree in Electrical Engineering Skilled in FPGA design techniques, RTL Design, tools and processes. Minimum 5 years and above experience in digital design/verification, emulation/ FPGA prototyping and system validation. Verilog/SystemVerilog based verification experience at Subsystem and Full chip level. Experienced in transactor-based verification. Verification methodology like UVM/OVM knowhow is a plus. Knowledge of RTL language (e.g., VHDL, Verilog), in-circuit emulation, simulation acceleration and FPGA prototyping. Familiar with emulation/prototyping tools and methodologies. Real experience of mapping complex SOC design into multi-FPGA platforms/emulators and hands on experience with Synopsys ZEBU, Cadence Palladium, Siemens Veloce or HAPS A proven track record with emulation-based verification methodologies including ownership of a suitably complex emulation workflow environment. Well versed in model building for prototyping or emulation. Experience with STA/timing closure, wrapper creation, HDL simulation, synthesis, and memory modelling for prototyping/emulation. Working knowledge of Perl, Python & Shell scripts is a plus Experience with digital systems based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols. Experience with SOC boot flow, writing basic test cases, clocking and platform bring up in Emulators or Silicon desired Interested in and passionate about staying updated with tech trends. Excellent verbal and written communication skills to communicate issues, impact and corrective action.