DFT Engineer

Position: DFT Engineer

Experience: 5+ years Location: Bangalore, India Company: Mettlesemi Systems and Technologies Pvt Ltd Job Type: Full-Time

We are seeking a skilled Design-for-Test (DFT) Engineer to join our silicon design team for a high-impact engagement with a prestigious global client. The ideal candidate will have strong expertise in SoC-level DFT architecture, ATPG, MBIST, and scan-based methodologies, contributing to the design and validation of high-performance, testable, and reliable silicon.

About Us

Mettlesemi Systems and Technologies Pvt. Ltd. is a Bangalore-based deep-tech company driving innovation across three key verticals:

• Custom Silicon Solutions & Embedded Systems Design
• Secure Hardware Products for Authentication and Cybersecurity
• Ultra-Low-Latency FPGA Systems for FinTech and Critical Infrastructure

Our expertise spans the entire silicon lifecyclefrom RTL design, DFT insertion, and SoC validation to ASIC prototypingpositioning us as a trusted partner to leading global semiconductor clients. This opportunity falls under our Silicon Solutions and Services vertical, with a focus on DFT architecture and implementation for complex SoCs.

Key Responsibilities

• Develop and implement Design-for-Test (DFT) architectures for complex SoC designs.
• Drive scan insertion, boundary scan, compression, and memory BIST (MBIST) strategies.
• Generate and analyze ATPG test patterns and optimize for coverage and performance.
• Collaborate with RTL, synthesis, and physical design teams to ensure DFT rule compliance and timing closure.
• Participate in DFT verification, debug, and post-silicon bring-up.
• Develop and maintain scripting automation for DFT flow optimization (Python, Tcl, Perl, or Shell).
• Interface with ATE teams for pattern validation and production test support.
• Contribute to continuous improvement of DFT methodologies and workflows.

Required Skills & Experience

• Bachelors or masters degree in electrical, electronics, or computer science engineering.
• 5+ years of experience in DFT design and implementation for ASIC or SoC projects.
• Proven expertise in scan insertion, scan compression, MBIST, and boundary scan (JTAG).
• Hands-on experience with ATPG tools such as Mentor Tessent or equivalent.
• Strong understanding of DFT verification flows, static timing analysis (STA), and design closure.
• Proficiency in scripting languages (Python, Perl, Tcl, or Shell).
• Familiarity with RTL coding (Verilog/SystemVerilog) and synthesis flows.
• Strong analytical, debugging, and cross-functional collaboration skills.

Preferred Qualifications

• Experience with multi-vendor DFT tools and flows (Synopsys, Cadence, Siemens EDA).
• Exposure to post-silicon DFT bring-up and failure debug.
• Knowledge of UVM verification methodology and gate-level simulation.
• Experience working with ATE (Automatic Test Equipment) and production test flows.
• Strong problem-solving mindset with a focus on DFT quality and test coverage optimization.

Why Join Mettlesemi

• Work on cutting-edge silicon design and DFT technologies for global semiconductor clients.
• Opportunity to own end-to-end DFT development across IP and SoC levels.
• Collaborative, innovation-driven environment focused on technical excellence.
• End-to-end visibility into silicon product design, validation, and test.
• Competitive compensation and benefits package.

To Apply: Submit your resume and a brief cover note highlighting your DFT experience to careers@mettlesemi.com Subject: Application for DFT Engineer 5+ Years

Join a deep-tech company where your work enables better test coverage, faster bring-up, and more reliable silicon.

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