395 Emulation Jobs - Page 6

Looking for Siemens EDA ambassadors: PowerPro PV/CAE for Power Estimation /Optimization We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us - whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the Siemens EDA team, you will contribute to Siemens EDA by increasing efficiency and customer happiness Siemens EDA’s Power platform. This is an ambitious position that will assist in growing Siemens's EDA business in India. About the group: Calypto System Design "Central Engineering Group (CEG)" group. CSD works on cutting edge tools like PowerPro, Catapult etc. The Product Validation and Customer Support team of CEG ensures quality products, educated and satisfied customers in the market for High Level Synthesis. PowerPro is the commercially available RTL sequential power optimization and power analysis tool. We are a team driven with lots of energy, synergy and passion. Job Responsibilities: Work as an integral part of Product Validation and Customer Support team to validate and educate feature of PowerPro. Being the internal end-user of the tool, validate all features and report issues. Development of test plan and writing test cases. Take measures to improve quality of Product and test environment. Support and debug customer test design methodologies using our products. Participate in architecture reviews and involve in defining features prototyping. Get along with field teams to understand customer design flows requirements and propose measures to optimize and improve flow results. Analyse customer reported bugs and plug gaps in testing, incorporate newer designs/flows. Use technical expertise to respond to customer inquiries, demonstrate products. Provide field application support to customer. Role may involve interaction with customers on critical issues to narrow down the problem. Work on different methodology for customer scenario. Provide script-based solution for quick turnaround time. Work on RTL to GDS flow , Glitch, Veloce PowerPro, PowerPro optimization flows. Technical Skills (Must have): B.Tech (EE/ECE) or M.Tech (VLSI/Microelectronics) with working experience of 5+ Years. Good knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, RTL to GDS flow expertise, HDL Languages Verilog/VHDL/SV. Good understanding of low-power SOC design principles. Strong Debugging Skills is must. Experience with class of products like simulation, synthesis, Place & Route, etc. Excellent problem-solving and debugging capability. Technical Skills (Good to have): Low Power concepts, RTL/Gate Simulation and Emulation, SPEF, Different tech nodes. Knowledge of one of the scripting languages like Perl, Tcl. Python will be a plus. Knowledge of different tools like (DC, Fusion compiler, RTL Architect, Prime Power, Prime time, Zebu, joules, Gate sign off tools etc ) Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. We’ve got quite a lot to offer. How about you? We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday Accelerate transformation Hybrid

What You will Do: The MIG BEST (Baseline Engineering & System Test) team at Cisco has embarked on a groundbreaking journey with powerful technologies and Network Automation at the forefront. The high caliber team that prides itself on customer success, outcome orientation, happiness and positivity! The product line includes the industry leading Core, Edge, Access & Optical portfolio and the respective evolutions. You are invited to embark on this incredible journey and lead this change. Role & Responsibilities: The successful candidate will be part of the MIG BEST (Baseline Engineering and System Test) organization with the responsibility to work on the solution strategy, test planning and design of the next generation networks for the SP Routing portfolio of XR based products. Key responsibilities will include: Design, Develop, automate and complete new HW or Features across complex Networks Implement Functional, Interoperability and customer use cases Define and qualify End to End / Solution Architectures, engage in debugging complex network problem and define solutions. Work on Network automation, algorithmic thinking and Analytics applications derived from customer use cases Work on continuous Improvement and Transformation with quality at the centre Collaborate optimally with teams across geographies in 3 + continents, direct customer interfacing and stakeholder management. Primary Skills Deeply passionate about quality and customer success Good Understanding of Service Provider technologies and architecture. Proven working knowledge of Networking protocols and L2 to L7 technologies (ISIS, OSPF, BGP, MPLS, L2VPN, L3VPN, EVPN, Segment Routing, SR-TE, SRv6, MPLS-TE, Multicast, SNMP, Network management tools), along with hands-on experience with Third party Traffic Generator/Emulation Tools. Dynamic experience in Software Quality Assurance with an incredible appetite to make products / solutions better Automation experience with Python, REST, Jenkins & Strong Linux fundamentals in an added advantage. Exposure to Data Models and Network manageability is highly desirable Strong written & verbal communication, and interpersonal skills Results oriented with a high degree of accountability, dedication and responsibility Qualifications and Requirements: BS/MS degree or equivalent in a relevant technical discipline such as EE/CS/ET combined with 8 -12 years of related experience in System and Solution testing or related software test experience. Excellent problem solving skills, familiarity with Linux and modern software tools and techniques for development/debugging and solid software design and development skills Industry certification such as CCNA/CCNP/CCIE/JCNA/JCIE will be a huge plus Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box! But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us! Message to applicants applying to work in the U.S. and/or Canada: When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco’s flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco’s Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible? As part of an extraordinary modem team, you’ll craft sophisticated & pioneering embedded firmware that deliver more performance in our products than ever before. You’ll work across subject areas to transform improved hardware elements into a single, integrated design. Join us, and you’ll help us innovate new wireless systems technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world. As a Cellular 5G/4G Physical Layer Firmware Engineer on this team, you will be at the center of the embedded 5G/4G/multimode cellular firmware effort within a silicon design group responsible for crafting and productizing state-of-the-art cellular SoCs. We are looking for someone comfortable with all aspects of embedded software development, who thrives in a dynamic multi-functional organization, is not afraid to debate ideas openly, and is flexible enough to pivot on constantly evolving requirements. Description - Implement key 3GPP protocols and control/data path processing algorithms with very tight time, latency and energy budgets by interfacing to specialized cellular ASIC hardware. - Examples of processing include 3GPP channels and procedures such as PDCCH, PDSCH,PBCH,PUCCH, PUSCH, PRACH, UL/DL HARQ, Tracking loops. - Examples of 3GPP algorithmic areas include: - Channel Estimation - Channel State Feedback - Interference Cancellation - Cell Search and Measurement - Beam Measurement - Work with systems engineers to refine signal processing algorithms for efficient firmware/hardware execution - Work with silicon designers to define HW interfaces, processors, bus, DMA, accelerator, and memory subsystems. - Specify, design, and implement the firmware architecture of an innovative mobile wireless communications system. - Assist in the development of pre-silicon emulation systems/virtual platforms and use them for pre-silicon FW design and HW verification. - Evaluate and implement pioneering tools for build, formal verification and test. - Define methodologies and best practices. Minimum Qualifications Experience with hardware control for physical layer4G/5G data path processing Understanding of 5G and 4G 3GPP protocols Experience implementing digital signal processing algorithms using special purpose digital signal processing HW. Strong understanding of linear algebra and digital signal processing principles. Deep understanding of software engineering principles, and core computer science fundamentals. Fundamental facility with C and C++, compilers, build and source code control tools. Significant experience with memory constrained Real Time Operating Systems (RTOS) and concurrent programming. Solid understanding of computer architecture with particular emphasis on the HW/SW interfaces of high speed communication subsystems. Experience with silicon prototyping, emulation systems, and virtual platforms. Proficiency debugging embedded software systems. Familiarity with UARTs, JTAG, and oscilloscopes. Some mainstream OS application level development and Python or Perl scripting experience. Preferred Qualifications Bachelor’s degree in electrical engineering, electronics and telecommunications, computer engineering or computer science is required. Submit CV

Responsibilities: Hands-on experience with ZeBu or Palladium emulators Strong RTL understanding (SV/UVM) and SoC knowledge Experience in pre-silicon validation and hardware/software co-emulation Familiarity with waveform, simulator, and debug tools

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role We are currently seeking a highly skilled verification engineer for GFX sub-system(Graphics Power Management) verification team. The Person A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Key Responsiblities Work with all partners such as lead architects and block design teams to understand features to be implemented and verified. Develop robugs test plan for both synthetic and real workload trace Debug verification test failures, working with the design teams Make sure the design meets functional/performance/power expectations Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and do test plan, test creation and triage, coverage, and assertion etc. Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail. Must have good English hearing, speaking, reading, and writing capabilities. Must have good teamwork and interpersonal skills. Graphics Pipeline Experience Is Preferred. Deep knowledge of computer architecture is preferred. Must be a self-starter, and able to independently drive tasks to completion. Preferred Experience Good teamwork and communications skills are required. Minimum 12 Years Of Experience In ASIC Verification Must be proficient in Verilog, System Verilog, UVM Methodologies, and C/C++ programming Academic Credentials B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering / Computer Engineering with Digital Systems/VLSI as major with 12+ Years of Exp Location : Hyderabad, India Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job Title: Lead FPGA Design Engineer Experience Required: 6+ years Location: Hyderabad/Bangalore Job Type: Full-time Industry: Semiconductor / Electronics / Embedded Systems Job Summary: We are looking for a highly skilled and experienced Lead FPGA Design Engineer to join our hardware design team. The ideal candidate will lead the design, implementation, verification, and validation of FPGA-based systems for complex hardware products. This role involves mentoring junior engineers, collaborating with cross-functional teams, and ensuring delivery of high-performance, high-reliability designs. Key Responsibilities: Lead architecture definition and design of complex FPGA solutions using VHDL/Verilog/SystemVerilog. Translate system-level requirements into FPGA design specifications. Hands-on implementation of FPGA designs using Xilinx, Intel (Altera), or Lattice FPGAs. Develop testbenches and perform simulation using tools like ModelSim, Questa, or VCS. Integrate and validate FPGA designs on hardware, working closely with board design and software teams. Use industry-standard tools such as Vivado, Quartus, Synplify, etc. Lead FPGA timing closure, floor planning, and resource optimization. Perform version control, documentation, and design reviews. Guide and mentor a team of junior engineers; ensure design best practices and quality processes are followed. Required Skills and Experience: Bachelor’s or Master’s degree in Electronics/Electrical/Computer Engineering. 6+ years of industry experience in FPGA design and verification. Expertise in VHDL/Verilog/SystemVerilog coding and simulation. Experience with FPGA toolchains such as Xilinx Vivado, Intel Quartus, Synplify. Strong knowledge of high-speed interfaces (e.g., PCIe, DDR, Ethernet, AXI). Familiar with embedded processor systems (MicroBlaze, Nios II, ARM SoCs). Proficiency in scripting (Tcl, Python, Shell) for automation. Experience with static timing analysis, constraints definition (SDC), and debugging. Good understanding of hardware/software integration. Excellent leadership, problem-solving, and communication skills. Preferred Qualifications: Prior experience in leading FPGA teams or projects. Exposure to safety-critical or mission-critical design environments (e.g., automotive, aerospace, medical). Experience with hardware emulation or ASIC prototyping on FPGAs. Familiarity with version control systems (Git, SVN) and documentation tools. Why Join Us? Work on cutting-edge FPGA designs in a collaborative environment. Competitive compensation with leadership opportunities. Growth-focused, innovation-driven engineering culture. Interested can share CV to sharmila.b@acldigital.com

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in AI Accelerators DNN Accelerators co-processors Interconnect Fabric Cache Coherency D2D C2C SoC Director Bangalore We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for embedded Edge AI vision-based applications and real-time data processing. Company has working HW & SW for customer sampling, with production designs in the pipeline, and a system architecture designed a future of neuromorphic computing. We are backed by excellent VC funding and is currently in a stage of rapid growth. While our tech is one of a kind we would not be able to make these advancements without our team. Our collaborative culture is one of the keys to our success. Who You Are You are an open and honest communicator who values your team You are innovative, enjoy bringing new ideas to the table and are receptive to ideas and feedback from others You’re passionate about advancing the state of the world through new technology You enjoy the ambiguity and pace of a startup environment The role This leadership role will be responsible for the global VLSI efforts at and It is a highly visible role reporting to Senior Director with ownership of all pre/post Si activities, leading interface with external EDA, IP, Design Service partners, managing the and a global VLSI team. What you will be doing: Ownership of pre-Si Design of the next-gen AI accelerator at driving deliverables with Design and IP Service providers, CAD tools, IPs, DFT/PD/Packaging and Test. Work closely with internal Architecture, SW, Emulation, and system board designers on product definition, microarchitecture, and design implementation. Build and manage the VLSI team of front-end design and verification engineers across India and Taiwan. Establish best practices for development, testing, reviews, and documentation. Participate in strategic discussions for product features and roadmap. What we expect to see: BS/MS in Electrical/Electronic Engineering with 18+ years of experience in VLSI, SOC design, several Si tape-out/production. Hands-on experience in front-end design, VLSI flows, and working experience for all aspects of Si tape-out, post-Si validation. Self-driven, organized with strong leadership and communication skills. Experience in building and managing teams with the ability to motivate and lead in a startup environment. Proven track record in several successful productizations. What we would be happy to see: Knowledge of AI, specifically Deep Neural Networks Application-specific accelerators or co-processors Startup experience Hours: Full time /3 days office-onsite Employment Opportunity and Benefits of Employment: We are committed to creating and fostering a diverse and inclusive workplace environment for all of our employees. We are an equal opportunity employer. Contact: Uday Mulya Technologies Email: muday_bhaskar@yahoo.com

Hello Visionary! We empower our people to stay resilient and relevant in a constantly changing world. We’re looking for people who are always searching for creative ways to grow and learn. People who want to make a real impact, now and in the future. Does that sound like you? Then it seems like you’d make a great addition to our vibrant team. We are looking for a Penetration Tester. This position is available for Chennai Location. You’ll make a difference by: Having experience in Leading and performing complex penetration testing engagements across enterprise networks, cloud infrastructures, web, mobile, APIs, thick clients, and IoT environments. Having understanding to Simulate sophisticated real-world attacks (e.g., APT scenarios, lateral movement, chained exploits). Conducting Red Team exercises and adversary emulation based on frameworks like MITRE ATT&CK. Identifying and exploiting vulnerabilities using both automated tools and advanced manual techniques. Reviewing, enhancing, and developing custom scripts, tools, and exploits to support internal testing capabilities. Providing expert-level guidance to business units on security risks, remediation strategies, and secure architecture. Actively participating in client discussions, executive briefings, and technical workshops. Delivering detailed and executive-level reports, including risk ratings, business impact, PoCs, and mitigation steps. Maintaining robust documentation of testing methodologies, custom tools, and process improvements. Ensuring all engagements align with internal policies, industry frameworks (e.g., OWASP, NIST, ISO), and client-specific compliance standards. Training and Development Stay updated on the latest security trends, vulnerabilities, and technology advancements. Provide training and guidance to the team and other departments on security best practices. Strategy and Planning Plan and scope penetration testing engagements, ensuring comprehensive coverage and effectiveness. Participate in the development of security policies and standards. Technical Expertise Deep hands-on experience in: Web, API, Thick Client and mobile app security testing (e.g., OWASP Top 10 – Web, Mobile, API) Internal/external network penetration, privilege escalation, and lateral movement Active Directory assessments and exploitation (Kerb roasting, Pass-the-Hash etc.) Familiarity with ICS, SCADA, BACnet protocols, and covert communication channels Wireless, Bluetooth, IoT device, Embedded Security, Cloud (AWS/Azure/GCP), and container security testing Working knowledge of Kali Linux and frameworks like MITRE ATT&CK Basic understanding of AI/ML security: adversarial attacks, model poisoning, and secure deployment of AI systems Proficiency with tools such as: Offensive: Burp Suite Pro, Metasploit, SQLMap, Cobalt Strike, Impacket, CrackMapExec, BloodHound, Sliver Reconnaissance: Nmap, Amass, Shodan, OSINT frameworks/tools Vulnerability Scanners: Nessus, Qualys, Nexpose Programming/Scripting: Skilled in scripting and exploit development using Python, Bash, PowerShell, and occasionally C/C++ or Go Soft Skills Excellent written and verbal communication skills Strong analytical and problem-solving capabilities Ability to explain technical concepts clearly to non-technical stakeholders You’ll win us over by: Having An engineering degree B.E/B.Tech/M.E/M.Tech with good academic record. 6–7 years of proven experience in penetration testing and offensive security Certifications (Preferred): Highly Desirable: OSCP, OSWP, OSWE, GPEN, GWAPT, OSCE, OSEE, GXPN, CPTS, CWEE, CAPE Other Considered: EWPTXv2 or equivalent advanced offensive security certifications We’ll support you with: Hybrid working Opportunities. Diverse and inclusive culture. Great variety of learning & development opportunities. Join us and be yourself! We value your unique identity and perspective, recognizing that our strength comes from the diverse backgrounds, experiences, and thoughts of our team members. We are fully committed to providing equitable opportunities and building a workplace that reflects the diversity of society. We also support you in your personal and professional journey by providing resources to help you thrive. Come bring your authentic self and create a better tomorrow with us. Make your mark in our exciting world at Siemens. This role is based in Chennai and is an Individual contributor role. You might be required to visit other locations within India and outside. In return, you'll get the chance to work with teams impacting - and the shape of things to come. We're Siemens. A collection of over 319,000 minds building the future, one day at a time in over 200 countries. Find out more about Siemens careers at: www.siemens.com/careers

Hello Visionary! We empower our people to stay resilient and relevant in a constantly changing world. We’re looking for people who are always searching for creative ways to grow and learn. People who want to make a real impact, now and in the future. Does that sound like you? Then it seems like you’d make a great addition to our vibrant team. We are looking for a Penetration Tester. This position is available for Chennai Location. You’ll make a difference by: Having experience in Leading and performing complex penetration testing engagements across enterprise networks, cloud infrastructures, web, mobile, APIs, thick clients, and IoT environments. Having understanding to Simulate sophisticated real-world attacks (e.g., APT scenarios, lateral movement, chained exploits). Conducting Red Team exercises and adversary emulation based on frameworks like MITRE ATT&CK. Identifying and exploiting vulnerabilities using both automated tools and advanced manual techniques. Reviewing, enhancing, and developing custom scripts, tools, and exploits to support internal testing capabilities. Providing expert-level guidance to business units on security risks, remediation strategies, and secure architecture. Actively participating in client discussions, executive briefings, and technical workshops. Delivering detailed and executive-level reports, including risk ratings, business impact, PoCs, and mitigation steps. Maintaining robust documentation of testing methodologies, custom tools, and process improvements. Ensuring all engagements align with internal policies, industry frameworks (e.g., OWASP, NIST, ISO), and client-specific compliance standards. Training and Development Stay updated on the latest security trends, vulnerabilities, and technology advancements. Provide training and guidance to the team and other departments on security best practices. Strategy and Planning Plan and scope penetration testing engagements, ensuring comprehensive coverage and effectiveness. Participate in the development of security policies and standards. Technical Expertise Deep hands-on experience in: Web, API, Thick Client and mobile app security testing (e.g., OWASP Top 10 – Web, Mobile, API) Internal/external network penetration, privilege escalation, and lateral movement Active Directory assessments and exploitation (Kerb roasting, Pass-the-Hash etc.) Familiarity with ICS, SCADA, BACnet protocols, and covert communication channels Wireless, Bluetooth, IoT device, Embedded Security, Cloud (AWS/Azure/GCP), and container security testing Working knowledge of Kali Linux and frameworks like MITRE ATT&CK Basic understanding of AI/ML security: adversarial attacks, model poisoning, and secure deployment of AI systems Proficiency with tools such as: Offensive: Burp Suite Pro, Metasploit, SQLMap, Cobalt Strike, Impacket, CrackMapExec, BloodHound, Sliver Reconnaissance: Nmap, Amass, Shodan, OSINT frameworks/tools Vulnerability Scanners: Nessus, Qualys, Nexpose Programming/Scripting: Skilled in scripting and exploit development using Python, Bash, PowerShell, and occasionally C/C++ or Go Soft Skills Excellent written and verbal communication skills Strong analytical and problem-solving capabilities Ability to explain technical concepts clearly to non-technical stakeholders You’ll win us over by: Having An engineering degree B.E/B.Tech/M.E/M.Tech with good academic record. 6–7 years of proven experience in penetration testing and offensive security Certifications (Preferred): Highly Desirable: OSCP, OSWP, OSWE, GPEN, GWAPT, OSCE, OSEE, GXPN, CPTS, CWEE, CAPE Other Considered: EWPTXv2 or equivalent advanced offensive security certifications We’ll support you with: Hybrid working Opportunities. Diverse and inclusive culture. Great variety of learning & development opportunities. Join us and be yourself! We value your unique identity and perspective, recognizing that our strength comes from the diverse backgrounds, experiences, and thoughts of our team members. We are fully committed to providing equitable opportunities and building a workplace that reflects the diversity of society. We also support you in your personal and professional journey by providing resources to help you thrive. Come bring your authentic self and create a better tomorrow with us. Make your mark in our exciting world at Siemens. This role is based in Chennai and is an Individual contributor role. You might be required to visit other locations within India and outside. In return, you'll get the chance to work with teams impacting - and the shape of things to come. We're Siemens. A collection of over 319,000 minds building the future, one day at a time in over 200 countries. Find out more about Siemens careers at: www.siemens.com/careers

Job Title: Design Verification Lead Location: Bangalore/Hyderabad Experience: 7+yrs Job Type: Full-time Industry: Semiconductors / VLSI / EDA Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE or related field Job Description: We are looking for a passionate and experienced Design Verification Lead to drive the verification of complex SoC/IP designs. The ideal candidate will have deep expertise in functional verification methodologies and will be responsible for managing a team, defining verification strategies, and ensuring high-quality silicon delivery. Key Responsibilities: Own and lead verification activities for IP or SoC-level designs. Define and execute the verification plan, test strategy, and coverage goals. Develop and manage verification infrastructure (testbenches, stimulus, checkers, etc.). Collaborate with RTL design, DFT, PD, and firmware teams. Mentor and lead a team of verification engineers. Perform reviews of testbenches, test cases, and coverage reports. Drive simulation-based verification using SystemVerilog, UVM. Track and report project progress and debug issues independently. Participate in regression setup and continuous integration for verification. Deliver high-quality verified RTL to meet tape-out schedules. Required Skills: 7+ years of experience in ASIC/FPGA verification. Strong expertise in SystemVerilog and UVM . Hands-on experience in developing complex verification environments. Good understanding of coverage-driven verification (functional and code) . Experience with scripting languages (Perl/Python/Tcl). Knowledge of protocols like AXI, AHB, PCIe, USB, DDR, etc. Familiarity with formal verification is a plus. Strong debugging skills using waveform tools like DVE, VCS, or ModelSim. Prior experience in leading teams and driving project deliverables. Good to Have: Experience in Emulation/FPGA prototyping. Exposure to low-power verification (UPF). Knowledge of verification IPs and reuse methodologies. Hands-on with gate-level simulations and performance verification. Soft Skills: Excellent communication and interpersonal skills. Ability to lead and mentor junior engineers. Strong problem-solving and analytical thinking. Ability to work in cross-functional and global teams. Interested can share CV to sharmila.b@acldigital.com

Job Summary: We are seeking a seasoned Mainframe Modernization Expert to lead and execute modernization initiatives that transition legacy mainframe applications to modern platforms. The ideal candidate will possess a deep understanding of mainframe environments (COBOL, CICS, JCL, DB2, etc.) and experience with cloud migration, rehosting, refactoring, or rewriting strategies using modern architectures like microservices, containers, and APIs. ________________________________________ Key Responsibilities: Assess current mainframe systems to identify modernization opportunities. Define and lead end-to-end modernization strategy and roadmap. Perform mainframe code analysis and determine the best-fit modernization approach (replatforming, rehosting, refactoring, or rewriting). Guide teams in converting COBOL and other legacy code to Java, .NET, or other modern languages. Collaborate with cloud and DevOps teams to integrate mainframe components into CI/CD pipelines and cloud-native platforms (AWS, Azure, GCP). Support data migration efforts from mainframe databases (e.g., DB2) to modern data stores (e.g., SQL, NoSQL, cloud-native DBs). Ensure security, performance, and reliability standards are met during and after modernization. Provide leadership and mentoring to technical teams throughout project lifecycles. ________________________________________ Required Skills and Qualifications: 10+ years of experience in mainframe technologies (COBOL, JCL, CICS, VSAM, DB2, etc.). 5+ years of hands-on experience with mainframe modernization projects. Proven expertise with at least one modernization approach (e.g., replatforming to Linux, rearchitecting to microservices, cloud-native conversion). Familiarity with mainframe emulation platforms (e.g., Micro Focus, IBM z/OS Connect, Raincode). Experience working with cloud platforms (AWS, Azure, GCP). Strong understanding of modern development frameworks and CI/CD tools. Excellent problem-solving and analytical skills. Strong communication and stakeholder management abilities. ________________________________________ Preferred Qualifications: Experience with code transformation tools (e.g., Heirloom, Modern Systems, Astadia). Experience with containerization (Docker, Kubernetes) and serverless architecture. Mainframe performance tuning and optimization background. Certifications in cloud technologies or modernization frameworks. Your future duties and responsibilities Required qualifications to be successful in this role Together, as owners, let’s turn meaningful insights into action. Life at CGI is rooted in ownership, teamwork, respect and belonging. Here, you’ll reach your full potential because… You are invited to be an owner from day 1 as we work together to bring our Dream to life. That’s why we call ourselves CGI Partners rather than employees. We benefit from our collective success and actively shape our company’s strategy and direction. Your work creates value. You’ll develop innovative solutions and build relationships with teammates and clients while accessing global capabilities to scale your ideas, embrace new opportunities, and benefit from expansive industry and technology expertise. You’ll shape your career by joining a company built to grow and last. You’ll be supported by leaders who care about your health and well-being and provide you with opportunities to deepen your skills and broaden your horizons. Come join our team—one of the largest IT and business consulting services firms in the world.

Bangalore, India • Full Time Meta Infrastructure Hardware The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Design Responsibilities Architecture exploration Micro-architecture development Soft and hard IP identification, selection and integration Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of silicon development experience with experience of first-pass success in ASIC (Application-Specific Integrated Circuit) Development Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs (Intellectual Properties), OR Experience in SoC (System on Chip) Micro-architecture, Design and Integration, OR Implementation, Power methodology development Experience with Verilog or System Verilog Lint, CDC (Clock Domain Crossing), Synthesis and Power Optimization Preferred Qualifications 15+ years of experience in silicon development Experience in data path development Experience in CPU, NOC (Network on Chip), Memory and Peripheral Subsystems Experience in HLS (High-Level Synthesis) Experience with Synthesis, Timing Closure and Formal Verification Methodology Experience with Power Analysis and Optimization Experience with scripting languages (TCL, Python, Perl, Shell-scripting) Experience working across multiple projects About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

Bangalore, India • Full Time Meta Infrastructure Hardware The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl/Python, TCL, and Make About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

Type of Hire External or Internal Job Description The application window is expected to close on: March 31, 2025 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Global Demonstration Engineering is the world class leader in delivering innovative, demonstration-centric experiences of Cisco solutions to customer providing a full-suite, integrated sales-enablement portfolio. By demonstrating to customers how Cisco products can make them more productive, sales teams and partners can enlarge sales opportunities and shorten the sales cycle. From scripted, repeatable demos to fully customizable labs with complete administrative access, the Cisco dCloud platform provides content and access to field and channel partners on any network (internal & external), any device and in any location. The dCloud Platform is a force that can not only improve people’s experiences but can also drive business. Your Impact The Proof-of-Concept Specialist is an SE role who will be responsible for the development, planning, design, delivery & coordination of Customer Proof of Concept Labs, mainly Enterprise Networking / NX but could include other technologies as well, for both internal and external audiences. This person will work extensively with BU’s, Content Developers, Partners, both internal & 3 rd party throughout the POC process from introduction through build, test and ultimately throughout the customer delivery of the POC. This person will be responsible for working with account teams to flesh out customer care abouts, testing requirements, capabilities, etc. Minimum Qualifications 1-2 years of experience of Strong Routing, Switching, and Security background. Cloud Networking Experience (AWS, Azure, GCP), Microsoft Office365 Experience with Virtual Infrastructures (VMware VCenter and VMs) Experience with Test Tools such as Spirent, Cyberflood, Avalanche, Ixia, Keysight, WAN Emulation. OSPF, EIGRP, BGP, MPLS, DMVPN, IPSec, NAT, Trustsec, LISP, VXLAN, EVPN, 802.1x etc. Preferred Qualifications Project Management and Time Management abilities Cisco Catalyst SD-WAN Experience Cisco Software Defined Access Experience Cisco Catalyst Center (DNA Center) Deployment and management Cisco SD-Access Fabric #WeAreCisco #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description Create System and FPGA designs to exercise all the use models targeted for each product mimicking end applications in a customer setting. Write system and product level validation plans for new and existing silicon products and projects; execute per plan, record and communicate results FPGA prototyping and emulation. Understanding spec., writing emulation plan and executing per plan. Record and communicate results. Understand hardware architectures, use models and system level design implementations required to utilize the silicon features. Be an effective contributor in a cross-functional team-oriented environment. Write high quality code in Verilog, VHDL and C code for embedded processors. Maintain existing code. Learn new system designs and validation methodologies. Understand FPGA architectures. o Be conversant with on-chip debug tool Requirements/Qualifications Qualifications/Requirements Excellent verbal and written communication skills in English 2+ Years experience in Design with RTL coding in Verilog and VHDL and Verification of RTL Possess an in-depth understanding of hardware architectures, system level IC design implementation, knowledge of how to create end use scenarios Optimizing code for FPGA architectures Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE Working knowledge on embedded software C/C++ is also a plus Strong technical background in FPGA prototype emulation, and debug Strong technical background in silicon validation, failure analysis and debug Excellent Board level debug capabilities in lab environment : hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal Design with RTL coding in Verilog and VHDL is a must Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools Hands-on systems level design and debug experience with at least two of the following high-speed serial communications protocols: i. PCIe Gen1/2/3 ii. Interlaken (10.3125 Gbps) iii. CPRI (614.4Mbps – 12.672 Gbps) iv. SGMII or QSGMII v. XAUI or HiGig/+/II vi. 10GBASE-R/-KR vii. Serial Rapid IO Travel Time 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re building high-performance RISC-V CPUs from the ground up, and we need someone who can help us test them thoroughly and thoughtfully. As a testbench lead, you'll design and maintain the infrastructure that makes sure our cores behave exactly as intended. If you enjoy figuring out how things break (and fixing them), building clean and reusable systems, and working with a team that values both rigor and creativity, we’d love to talk. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You’ve built and maintained testbenches for CPU cores or similar designs, using SystemVerilog, UVM, and C++. You like creating clean, reusable components — from transactors to functional models — that others can plug in and build on. You’re comfortable working across both software-style C++/UVM environments and hardware-style simulation flows. You enjoy collaborating with design teams and helping them debug issues quickly and clearly. What We Need Someone to design and grow a UVM testbench setup that works for both block-level and full-chip simulation. The ability to write C++ code that fits into a DV framework — and help shape that framework as it evolves. A good understanding of CPU microarchitecture and how to test it effectively. Comfort working across tools, from open-source simulators like Verilator to commercial environments and emulators. What You Will Learn How to design testbenches that scale with complexity — and keep them maintainable as the chip grows. How to support both simulation and emulation from the same DV infrastructure. How custom C++ and UVM environments can coexist to improve verification workflows. How different teams — RTL, DV, software, tools etc — come together to build AI-focused silicon. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Job Title R&D Engineer I (PLC) Job Description Our company Vanderlande is the global leader for value-added logistic process automation at airports and in the parcel market, as well as a leading supplier of process automation solutions for warehouses. In this world of technology, we believe in people – especially those who are totally dedicated, customer-driven and keen to continue learning throughout their career. If you’re ambitious and take your long-term career seriously, then please contact us to explore this opportunity. For more information or to apply for this challenging position, please visit www.vanderlande.com Your department Vanderlande’s product/module development department Development Center Equipment (DCE) India (formerly Research & Development India) collaborates globally with technology centres at Netherlands, Germany, Spain, and North America. DCE technology center plays a key role in the continuous investment in developing new products and leverage technologies to strengthen company position and differentiate Vanderlande products in material handling automation solutions market. Your role Senior R&D engineer is an integral member of a global agile stream and shares responsibilities with development engineers’ being part of the scrum team. In this position you will work in a multi-disciplinary group of mechanical, electrical, controls (PLC) and software engineers. You will report to the Group Leader/Development Manager in DCE India. Your qualification BE. / B. Tech/ M.E / M. Tech (Electrical, Electronics, Computer, Instrumentation, or allied engg. branch) from a recognized University / Institution. Professional Experience 5-8 years of relevant industry experience, out of which at least 3 years with PLC control material handling automation solutions. Tasks And Responsibilities Hands-on experience of Siemens S7-300/400/1200/1500 series PLC systems. Expert in working with Step7/TIA Portal software and simulation environment. Proficient in popular programming methods such as Statement List (STL), Structured Control Language (SCL), Ladder logic, and Functional Block Diagrams (FBD). Experienced in HMI and SCADA (WinCC) systems. Practical knowledge of field bus systems (ASi, Profibus, Profinet, ProfiSafe, Ethernet/IP, DeviceNet, ControlNet). Excellent command on fundamental programming concepts, basic principles, and related terminologies to write code, which is simple to understand, modular and efficient. Awareness of programming techniques such as variables, basic control structures, data structures, object-oriented programming, troubleshooting, debugging, and various programming tools. Parameterization and application knowledge of variable frequency drives, motor controllers. Design concepts and translates them into standard application and design rules at equipment and system level. Study(analyse) and read module books for effective design solution. Work on development of new PLC code, build/add on standard library blocks for new function integration. Generate configurable functional blocks and secure developed software. Provide accurate time estimates to plan and deliver own work. Create and release standard product deliverables. Identify and Documenting Risks, and work on solutions. Work on multiple test scenarios to execute exception handling, unit and integrated system tests by running them using emulation environment or on proto equipment under development. Familiar with product development life cycle. Ensure process conformity, quality, and timely delivery of committed tasks. Contribute to competence development, spread domain specific knowledge. Skills Excellent interpersonal, verbal, and written communication skills – English language. Taking initiative, supportive, creative problem-solving skills. Flexible, naturally adjustable when situation demands. Innovative mind-set and drive for continuous improvement. Collaborative – multilingual and multicultural team setups. Ownership – take personal responsibility. Team player – works together as a team. Enthusiastic, energetic, and passionate about advanced technologies. Assertive and able to achieve effective results. Proactive, self-driven and ability to work independently. Functional knowledge of Enovia or any PLM tool. Practical expertise of Atlassian tool suits (Jira, Confluence, Bitbucket, SourceTree, Bamboo). Knowledge of Microsoft Office Suite (MS word, MS excel, MS outlook and MS teams app). Experience of executing work in Agile environment is an added advantage

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: S ENIOR SOFTWARE DEVELOPMENT ENGINEER THE ROLE: AMD is looking for a specialized software engineer to join our growing team. You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technologies. As a key contributor you will be part of a leading team to drive and enhance AMD’s abilities to deliver the highest quality, industry-leading technologies to market. THE PERSON: The ideal candidate should be passionate about software engineering, have good understanding of the underlying hardware and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Primary responsibility is the validation of Bootloaders, which includes the following tasks: Develop and execute test cases to validate all boot peripherals from where the FSBL (First Stage Boot Loader) is copied. Example: xSPI, SD, eMMC, UFS, USB Create and execute test cases to validate all proprietary boot sequences. Develop and execute test cases to validate all internal boot modes. Develop and execute test cases to validate all supported encryption/decryption algorithms. Automate tests using Python. Perform testing on prototyping/emulation platforms, including X86 emulation. Report coverage metrics using tools such as Verdi and add tests to ensure maximum source line coverage. Review requirements and create associated test cases to ensure traceability. PREFERRED EXPERIENCE: 5-8 years of experience, Proficiency in C, Python Good understanding of ARM architecture and knowledge of ARM based SoCs Good understanding of various boot peripherals- xSPI, SD, eMMC, UFS, USB Experience with Windows, Linux and/or any RTOS Experience developing bootloaders and drivers for hardware cyrpto accelerators is a plus Experience in developing software, that is certified for Safety and Security, is a plus Effective communication and problem-solving skills ACADEMIC CREDENTIALS: Bachelor’s or Master's degree in Electronics and Communication Engineering or Computer Science and Engineering, or equivalent #LI-SK4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: THE ROLE: AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Board bring-up activities for Software components like bootloader, (Secure Bootloader components like Crypto Engines etc., platform managers (Power management, Clock management , system restarts/shutdowns etc.) Bring-up activities for Software stack for Linux and baremetal including Applications for ARM based boards and emulation platforms, Proto-typing platforms Develops and execute test plans to evaluate functionality, security, and efficiency of firmware utilizing emulation and evaluation boards for pre-silicon and post silicon verification. Analyzes, tracks, and debugs testing failures to determine corrective measures. Collaborates directly with development team to assess test plan requirements and resolve failures. Automate and the functional and System level tests using Python and integrate the same in Test Automation framework and maintain the Test artifacts for any updates in the Test cases or in Test framework Run the Regression tests, triage issues, create Defects in the system and wok with development team for closure. Drive dynamic code coverage for boot level Firmware using standard tools like LDRA etc. PREFERRED EXPERIENCE: 5- 12 years of experience in Baremetal or Linux Kernel internals/driver development/application development. Proficient in C/C++ and embedded systems. Working experience in verification and testing of Embedded System software or firmware etc. Good experience in Device Driver Verification and validation on Linux, Bare metal, Real Time Operating Systems. Skills in compiling/building/cross-compiling, debugging, testing, deploying Bootloader, TF-A, Linux Kernel, Device tree, Middleware software, and BareMetal application images for board bring up activities through JTAG debuggers & Emulators using different boot modes Good understanding of any one of SoC/Processing Technologies like ARM/RISC-V/X86, MMU, Interrupt handling, Caches etc. Hands on with one or more peripherals/controllers like UART, I2C, SPI, USB, SD, eMMC, QSPI, PCIe etc. Define, Design and Develop manual/Automation test cases for Embedded system projects Programming skills in C/C++, Makefile, Linker file creation, scripting language Python/Shell/Tcl Experience in GIT environment and Test Automation framework – Pytest, Jenkins etc. Good to have exposure in design tools like VIVADO, VITIS, Configuration management tools like GIT/Perforce, JIRA, Confluence etc ACADEMIC CREDENTIALS: Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent #LI-SK4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

We are seeking a skilled Verification Engineer to join our team. The successful candidate will be responsible for the verification of internally developed VTLs (Veloce-friendly standard protocols such as AMBA, PCIe, SAS, Ethernet, MIPI, etc.) using various standard verification methodologies, including UVM, and ensuring signoff based on coverage matrix. We are not looking for superheroes, just super minds You’re a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/VLSI from top reputed Engineering colleges with 5-8 years of significant experience in software development. Experience in EDA will be a phenomenal plus. Practical experience with any of the following protocols: PCI/PCIe or CXL. Experience in IP and SOC level verification. Knowledge of verification methodologies such as Specman, SV, UVM, OVM, TLM, Assertion, Coverage, co-simulation, and co-verification. Good interpersonal skills for working with external interfaces. FPGA/Emulation experience is helpful. Strong scripting and automation knowledge is a significant plus. Responsibilities: Develop and maintain UVM-based testbenches for verifying PCIe and CXL protocols. Create and execute detailed verification plans based on design specifications and protocol standards. Implement SystemVerilog assertions , coverage models, and functional tests. Integrate and utilize Verification IPs (VIPs) for PCIe/CXL (Gen3/Gen4/Gen5/Gen6). Join our Digital World! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, colour, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. At Siemens, we are always challenging ourselves to build a better future. We have some of the most inquisitive minds working across the world, re-imagining the future and doing outstanding things.

About the Company Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. About the Role Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Responsibilities Own end-to-end SOC RTL delivery while analyzing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Design Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 5+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

• Design Methodology, Micro-architecture, RTL. • Work with the architecture team to develop the uArch & Subsequently write RTL. • Develop Design Methodology, starting with the machine learning architecture. • Synthesis, STA, Equivalence checking. Required Candidate profile * EXP in SOC design methodology, Micro-architecture, Emulation & back-end DEV., & Chip Bring-up. * EXP in Developing ARM CPU based SoCs, Network-on-Chip & interfaces such as MIPI-CSI, Ethernet & PCIe

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

Position: Pre-Post Silicon Embedded Engineer Years of Experience: 10+ Years Location: Bengaluru, Karnataka Job Brief: Today, software is proliferating in every sector. Automotive, HPCs, Consumer electronics, etc. Name any domain, and you will notice huge lines of software code. It’s fair to say that soon, software will rule the world. One of the big challenges for system and silicon companies is to verify and validate their SoCs as early in the product design cycle as possible. Product teams are achieving this by performing what is called a “ shift left ”. In the context of chip verification and validation, it is tantamount to having device drivers/software. Engineers work as part of silicon validation teams and develop driver software to test the SoC, all its critical data paths, performance et al during pre-silicon verification itself. Job Description: Vayavya Labs is closely working with an industry leader in the consumer electronics space for the development of a device driver and bare metal software to verify and validate the customer’s cutting edge SoC. The job involves working with the pre- & Post silicon bringup teams. Understanding the SOC architecture (sub-systems like Camera/Display/GPU/memory/security modules, etc.) and developing the required test software. Ability and expertise in quickly understanding the sub-system architecture and the corresponding test plans is a must. The job also involves executing this software on emulation hardware and FPGAs in pre-silicon and the actual development board in post-silicon. You will be working with global teams, and this is an excellent opportunity to interact with the best in the world. You should be comfortable with C programming and scripting languages like Python and TCL. Must Have Skills: Deep understanding of PCIe Gen3/Gen4/Gen5 (and emerging Gen6) specifications, including transaction, data link, and physical layers. Proven experience in PCIe protocol-level validation, error injection, and compliance testing. Strong proficiency in C programming for embedded systems. Knowledge of ARM architecture and subsystems. Good to Have: Familiarity with ASIC verification methodologies and proven experience in verification processes. Experience with hardware emulators like Synopsys Zebu, Cadence Palladium, or Mentor Veloce. Knowledge of Pytest, TCL, and Bash scripting. Experience in consumer electronics, particularly in products involving displays and camera peripherals. Understanding of RTL-level verification techniques. Familiarity with FreeRTOS for real-time operating systems. Experience with Linux system programming (threads, mutexes) and ARM booting processes. Non-Technical Skills: Strong analytical and problem-solving skills. Excellent debugging and troubleshooting capabilities. Clear and effective verbal and written communication. Self-motivated with a strong ability to learn and adapt. Eager to take on new challenges and responsibilities.