6 Asic Methodology Jobs

As a skilled professional with a Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience, along with 6 years of expertise in ARM-based System on a chip (SoCs), interconnects, and Application-Specific Integrated Circuit (ASIC) methodology, you are well-equipped to take on the responsibilities of this role. Additionally, your 5 years of experience in Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture, coupled with your proficiency in a coding language like Python or Perl, make you an ideal candidate for this position. Ideally, you hold a Master's degree or a PhD in Electrical Engineering, Computer Science, or possess equivalent practical experience. Your 6 years of industry exposure in Intellectual Property (IP) design, familiarity with methodologies for RTL quality checks such as Lint, CDC, RDC, and expertise in low power estimation, timing closure, and synthesis further enhance your qualifications for this role. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in innovating products that are cherished by millions worldwide. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration. In this role, you will be responsible for designing foundation and chassis IPs (such as Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU), and other peripherals) for Pixel System on a chip (SoCs). Collaborating with cross-functional teams including architecture, software, verification, power, timing, and synthesis, you will be involved in specifying and delivering high-quality Register-Transfer Level (RTL). Your role will entail solving technical challenges related to micro-architecture, low power design methodology, and evaluating design options while considering performance, power, and area requirements. Google's mission to organize the world's information and make it universally accessible and useful is at the core of our work. By combining the best of Google AI, Software, and Hardware, we strive to create remarkably helpful experiences for our users. Our team is dedicated to researching, designing, and developing cutting-edge technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to improve people's lives through technology. Key Responsibilities: - Participate in test planning and coverage analysis. - Develop Register-Transfer Level (RTL) implementations aligning with power, performance, and area objectives. - Engage in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA) and silicon bring-up processes. - Conduct Verilog/SystemVerilog RTL coding, functional and performance simulation debugging, and Lint/CDC/FV/UPF checks. - Create tools and scripts to automate tasks and monitor progress effectively.,

As a member of the team at this organization, you will play a crucial role in the development of custom silicon solutions that will drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process that leads to the creation of products that are beloved by millions around the globe. Your expertise will be key in shaping the next generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, and a minimum of 3 years of experience in Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture, and automation, you are well-equipped to excel in this role. Additionally, you should have 3 years of experience with Register-Transfer Level quality check tool flows such as Lint, Clock Domain Crossing, Reset Domain Crossing, and Synthesis. Preferred qualifications include experience with methodologies for RTL quality checks, IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols, and ASIC methodology. Additionally, experience with methodologies for low power estimation, timing closure, synthesis, and knowledge in areas such as Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin Multiplexing would be advantageous. Your responsibilities will involve defining microarchitecture details for the integration of Intellectual Property's (IPs) at the macro/Sub-System Workload Requirements Plan (SSWRP) level. You will be engaged in RTL development using SystemVerilog, debugging functional/performance simulations, and conducting RTL quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, and Unified Power Format (UPF) checks. Furthermore, you will participate in synthesis, timing/power estimation, and FPGA/silicon bring-up processes. Join us in our mission to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create experiences that are radically helpful. By researching, designing, and developing new technologies and hardware, we aim to make computing faster, seamless, and more powerful, ultimately improving people's lives through technology.,

As a Senior ASIC RTL Design Engineer at Google, you will play a crucial role in shaping the future of custom silicon solutions that drive Google's direct-to-consumer products. Your expertise in RTL design will be instrumental in delivering innovative hardware experiences with superior performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience, and a minimum of 15 years of experience in ASIC RTL design, you are well-equipped to excel in this role. Your proficiency in Verilog/System Verilog and microarchitecture will be essential in contributing to the development of ARM-based SoCs, interconnects, and ASIC methodology. In addition to your technical skills, having a Master's degree in Electrical Engineering or Computer Engineering will be advantageous. Your experience in driving multi-generational roadmaps for IP development and leading interconnect IP design teams for low power SoCs will further enhance your capabilities. As part of our dynamic team, you will lead a group of talented individuals to deliver fabric interconnect design. Your responsibilities will include developing and optimizing RTL designs to meet power, performance, area, and timing requirements. You will define key details such as interface protocols, block diagrams, data flow, and pipelines while overseeing RTL development and conducting functional/performance simulations. Effective communication and collaboration with cross-functional and multi-site teams will be crucial in ensuring the successful execution of projects. By joining Google's Devices & Services team, you will have the opportunity to contribute to creating revolutionary technologies that enhance user experiences and make a positive impact on people's lives through cutting-edge hardware innovations.,

As a candidate for this role, you should hold a Bachelor's degree in Electrical/Computer Engineering or possess equivalent practical experience. You should also have at least 2 years of experience working with RTL design using Verilog/System Verilog and microarchitecture, particularly in the realm of ARM-based SoCs, interconnects, and ASIC methodology. A Master's degree in Electrical/Computer Engineering would be considered a preferred qualification for this position. Additionally, experience with methodologies for RTL quality checks (such as Lint, CDC, RDC) and low power estimation, timing closure, and synthesis would be beneficial. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that will power the future of Google's direct-to-consumer products. Your contributions to this team will play a crucial role in shaping the innovation behind products that are beloved by millions around the globe. Your expertise will be instrumental in defining the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration. Within our platform IP team, you will collaborate on designing foundation and chassis IPs for Pixel SoCs, including components such as NoC, Clock, Debug, IPC, MMU, and other peripherals. Your role will involve partnering with colleagues from various disciplines including architecture, software, verification, power, timing, and synthesis to specify and deliver RTL. You will be tasked with solving technical challenges using innovative micro-architecture, implementing low power design methodologies, and assessing design options based on complexity, performance, and power considerations. At Google, our mission is to organize the world's information and make it universally accessible and useful. By combining the strengths of Google AI, Software, and Hardware, our team strives to create profoundly helpful experiences. We engage in research, design, and development of new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately aiming to improve people's lives through technology. Your responsibilities in this role will include defining microarchitecture details such as interface protocols, block diagrams, data flow, and pipelines. You will be involved in RTL development using SystemVerilog, debugging functional and performance simulations, conducting RTL quality checks (including Lint, CDC, Synthesis, UPF checks), participating in synthesis, timing/power estimation, and FPGA/silicon bring-up, as well as collaborating with multidisciplinary teams across different locations.,

As a Senior ASIC RTL Design Engineer at Google, you will be a key member of a team dedicated to creating custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions globally. Your expertise will play a crucial part in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. As part of the Devices & Services team, you will have the opportunity to combine the best of Google AI, Software, and Hardware to create innovative and helpful user experiences. You will be involved in researching, designing, and developing new technologies and hardware to enhance user interactions with computing, making them faster, seamless, and more powerful. **Responsibilities:** - Lead a team to deliver fabric interconnect design for ASICs. - Develop and enhance RTL design to meet power, performance, area, and timing objectives. - Define key details such as interface protocols, block diagrams, data flow, and pipelines. - Oversee RTL development and debug functional/performance simulations. - Collaborate effectively with multi-disciplined and multi-site teams. **Minimum Qualifications:** - Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. - 15 years of experience in ASIC RTL design. - Proficiency in RTL design using Verilog/System Verilog and microarchitecture. - Experience with ARM-based SoCs, interconnects, and ASIC methodology. **Preferred Qualifications:** - Master's degree in Electrical Engineering or Computer Engineering. - Proven experience in driving multi-generational roadmap for IP development. - Experience in leading interconnect IP design teams for low power SoCs.,

Create and support innovative Design Methodologies by leveraging feedback from our EDA and Digital IP teams. Integrate Methodologies into the development infrastructures of the Digital IP teams and demonstrate successful results. Support and maintain our regression infrastructure to manage changes and revise methodologies regularly. Test a range of Digital IPs through our Methodologies centered around Synopsys EDA tools. Collaborate with various teams to improve methodologies, enhancing both team and customer experiences. Develop and manage infrastructures, processes, methodologies, and checklists for the SG Digital IP Controllers. The Impact You Will Have: Enhance the efficiency and effectiveness of Digital IP development processes. Ensure high-quality and robust Digital IP products through rigorous methodology testing. Improve customer satisfaction by delivering superior Digital IP solutions. Drive innovation in design methodologies, contributing to Synopsys leadership in the industry. Facilitate seamless integration of methodologies into development infrastructures, optimizing workflows. Support the continuous improvement of regression infrastructures, ensuring up-to-date methodologies. What You'll Need: Bachelor's or Master's degree in electronics or electrical engineering or equivalent from reputed universities. 6-10 years of relevant experience in ASIC/SoC/IP Methodology. Proficiency in Synopsys implementation and infrastructure tools (coreConsultant, coreAssembler, SpyGlass/VC-SpyGlass, Fusion Compiler/Design Compiler, Prime Time, Formality, TestMax Manager, TCM, Verdi, VCS). Familiarity with multi-clock designs and understanding of Clock-Domain-Crossing principles. Proficiency in scripting languages (TCL, Perl, Python).