What You'll Be Doing: Review SerDes standards to develop novel transceiver architectures and sub-block specifications. Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area, and performance targets. Work across project and department teams to streamline design and verification strategies ensuring overall design quality, efficiency, and performance. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present and review simulation data from internal project teams; present results externally at industry panels or customer reviews. Document design features and test plans; consult on the overall electrical characterization of the SerDes IP product. Analyze customer silicon data for design enhancements and propose solutions for post-silicon design updates. The Impact You Will Have: Contribute to the development of cutting-edge Multi-Gbps NRZ & PAM4 SERDES IP, shaping the future of high-speed communication technology. Drive revolutionary improvements in power, area, and performance, enhancing the overall efficiency and effectiveness of our designs. Streamline design and verification strategies across teams, fostering a collaborative and innovative work environment. Ensure high-quality design and performance through meticulous oversight of physical layouts and awareness of design for reliability and signal integrity issues. Enhance customer satisfaction by analyzing silicon data and proposing effective design updates. Represent Synopsys at industry panels and customer reviews, showcasing our commitment to excellence and innovation. What You'll Need: MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical Engineering, Computer Engineering, or a related field. Experience with FinFET technologies and a strong understanding of transistor-level circuit design and CMOS fundamentals. Extensive design experience with high-speed designs, including PAM4 SerDes architectures and various SerDes sub-circuits. Familiarity with tools for schematic entry, physical layout, design verification, and SPICE simulators. Exposure to scripting for post-processing of simulation results (e.g., TCL, PERL, MATLAB).

Specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores. Perform verification tasks for IP cores, working closely with RTL designers. Drive ownership of critical areas of verification along with a team of talented verification engineers. Develop and implement advanced test plans and test environments at both unit and system levels. Code and debug test cases, implementing complex checkers and assertions. Extract and review functional coverage (FC) and code coverage metrics, ensuring quality metric goals are met. Manage regressions and contribute to the continuous improvement of verification strategies and test environments. The Impact You Will Have: Enhance the quality and efficiency of our verification processes, ensuring robust and reliable IP cores. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enable the creation of high-performance silicon chips and software content, driving innovation in various industries. Collaborate with a global team of experienced verification engineers, fostering a culture of knowledge sharing and continuous learning. Play a key role in the success of Synopsys DesignWare IP Verification R&D team, contributing to our leadership in chip design and software security. What You'll Need: BS/MS in Electrical Engineering or Electronics and Communication Engineering with 8+ years of relevant experience. Proven experience in developing HVL (System Verilog/UVM) based test environments. Expertise in developing and implementing test plans, checkers, and assertions. Proficiency in extracting verification metrics such as functional coverage and code coverage. Experience with memory interface protocols (DDR, LPDDR) and IP design and verification processes.

Providing technical support to customers for SPICE/FastSPICE simulation and custom compiler frontend applications. Collaborating with Sales, R&D, Product Application Engineers, and Marketing to drive business growth. Understanding customer requirements and exploring business opportunities. Creating simulation flows and debugging technical issues. Leading technical benchmarks and customer engagements. Writing customer requirement specifications and conducting product training sessions. The Impact You Will Have: Enhancing customer satisfaction and loyalty through exceptional technical support. Driving the adoption and successful implementation of SPICE/FastSPICE simulation and custom compiler solutions. Improving product usability and performance based on customer feedback and insights. Fostering strong relationships with customers and understanding their needs and challenges. Collaborating with R&D teams to influence product development and innovation. Contributing to Synopsys reputation as a leader in technology and innovation. What You'll Need: Design and verification experience in clocking circuits (PLLs), data converters (ADCs, DACs), and other analog circuits. Experience in memory design and verification of SRAM, SRAM compilers, DRAM, Flash, or other non-volatile memories. Knowledge of competitive EDA tool products in digital, analog, and mixed-signal design and verification. Proficiency in English for written and verbal communication. Excellent communication, presentation, problem-solving, and project management skills. BSEE or equivalent with 8+ years of relevant experience, or MS/Ph.D. with 6+ years of relevant experience.

Working closely with customers to understand their requirements in verifying custom design IP. Tailoring solutions to address challenging verification scenarios for custom designs. Collaborating with the product team to define, test, and deploy new features. Providing technical support and expertise on Synopsys ESP equivalence check product. Conducting product demonstrations and training sessions for customers and partners. Developing and maintaining technical documentation and application notes. The Impact You Will Have: Enhancing customer satisfaction through effective technical support and custom solutions. Driving the adoption and integration of Synopsys ESP equivalence check product. Contributing to the continuous innovation and development of new product features. Ensuring the highest quality of custom designs by catching elusive corner case design inconsistencies. Building strong relationships with customers and fostering long-term collaborations. Expanding Synopsys market presence through successful customer engagements. What You'll Need: Bachelor's or Master's degree in Engineering/Technology (Electronics/Electrical or related field). 1-2 years of experience in custom design verification. Understanding of circuits at SPICE netlist level and design description in Verilog/System Verilog. Knowledge of transistor-level design and simulation in MOSFET technology. Excellent written and oral English communication skills.

Develop validation environment on various industry-based SoC design on Emulation/FPGA and/or Virtual environments. Collaborate with Design SoC, Solutions and Synopsys IP team. Collaborate across complementary teams to develop and trace system requirements, functionality and Performance environment. Align with the development work taking place across multiple teams. This includes steering the development of functional and performance test plans, environment and supporting the Emulation/FPGA, Solutions and IP team. Stay up to date with the latest advancements in semiconductor design and Emulation technology to drive innovation and continuous improvement. Mentor to junior engineers and team members Work with engineering teams to improve various workloads Required Skills & Experience: Bachelor's or Master's in Electronic Engineering, Electrical Engineering, Computer Engineering, VLSI, or related field. Minimum 8 years in SoC Validation. Have emulation experience in Zebu/Haps or equivalent platforms. Have HW RTL verification and debugging expertise. Design & Develop test environment having various debug hooks and automation. High speed protocols (such as USB, PCIe, UFS or LPDDR technology) knowledge/experience is a plus. Able to work independently with minimal supervision, Lead the team technically, Capable of mentoring and developing a strong team.

Optimize existing GPU implementations for ILT software. Design new GPU-accelerated algorithms for large-scale geometric data handling for ILT. Collaborate with cross-functional teams to ensure seamless integration of GPU features. Lead benchmarking and performance testing initiatives. Stay current on GPU technology trends and design the latest advancements into the system. Work closely with customers and hardware vendors to deliver optimal solutions rapidly. The Impact You Will Have: Enhance the performance and efficiency of ILT software through optimized GPU implementations. Develop innovative GPU-accelerated algorithms that handle large-scale geometric data efficiently. Ensure seamless integration of GPU features into existing Mask Synthesis tools. Lead performance testing to ensure the highest standards of software quality. Drive technological advancements by integrating the latest GPU trends into our systems. Contribute to the rapid manufacturing of new chips by delivering optimal solutions swiftly. What You'll Need: M.S. or Ph.D. in Computer Science or a related field. 6+ years of experience working with GPU-accelerated systems. Proficiency in CUDA, OpenCL, ROCm, or related technologies. Expertise in C++ and Python. Experience in distributed computing environments. Strong troubleshooting and collaboration skills.

What You'll Be Doing Responsible for PCIe/CXL next-gen Controller IP features Customer pre/post sales PCIe/CXL protocol related communication Utilizing advanced design methodologies and tools to achieve high-quality results Mentoring and guiding other engineers, promoting best practices, and fostering a culture of continuous improvement Communicating with internal and external stakeholders to align on project goals and deliverables. What You'll Need: Extensive experience in digital ASIC design and physical aware synthesis. In-depth knowledge of PCIe, CXL , AXI, CHI and similar IO protocols. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 20+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

Job Description: Central product engineering role to liaison between R&D, Field engineering teams, along with product engineers within and other product teams. Test new product features through alpha and beta phases, identify and document usage scenarios, conduct Beta testing with interested customer counterparts and ensure successful deployment of new differentiating features. Study and improve usability, applicability and adoption of products, platforms and solutions to meet customer business needs. Diagnose, troubleshoot and resolve complex technical issues on customer installations Deploy and train customers on new implementations and capabilities. Review and analyze feedback on product and solutions performance from customers and other application partners Work directly with Research and Development (R&D) to develop and implement technical roadmap, specifications and validation for improvements and enhancements. Partner with customer technical leaders and Sales to identify business challenges, develop effective technical solutions for new accounts and increase utilization and retention of products on current accounts. Demonstrate creativity in building effecting test scenarios to exercise product features and identify issues as early as possible in development and deployment life cycles. Handle customer escalated situations with calm demeanor and create alternative solutions to un-gate critical engagements and production stop scenarios. Requirements: Typically requires a minimum of 5 years of related experience. Possesses solid background in Spice simulations (HSPICE, FineSim and industry standard simulators) with ability to create and work with spice decks and netlists. Experienced in standard cell characterization and basic concepts of timing (NLDM, CCST, CCSN), power (NLPM, CCSP), noise (CCSN), LVF, AOCV/POCV methodologies. Resolves issues in creative ways. to create usable workarounds and alternative solutions. Exercises independent judgment in selecting methods and techniques to obtain solutions. Executes projects from start to completion. Contributes to moderately complex aspects of a project Determines and develops recommendations to solutions. Works on team-driven or task-oriented projects. Networks with senior internal and external personnel in own area of expertise. Collaborates across various related tools to provide a complete solution to customers. Possesses excellent communication and inter-personal skills.

Working on latest Synopsys implementation technologies ( Machine Learning , Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions Working with customers to develop and debug RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA Coming up with proactive understanding of customers pain point and come up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies This role requires you to act as customers advocate while talking to inhouse R&D, and be a product brand ambassador while engaging with customers. Requirements: At-least 10 years of experience in Physical Implementation RTL-GDS. Experience in unsupervised debugging and resolving synth & PnR implementation challenges. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage The person must be self-motivated and dedicated with solid debug skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including ability to interface with customers and business unit personnel are essential.

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Creating floorplans, routing, and performing physical verifications to meet quality standards. Debugging and solving complex layout issues to ensure high-quality deliverables. Collaborating with design engineers to optimize layout for performance, power, and area. Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. Ensuring compliance with DRC, LVS, ERC, and antenna rules. The Impact You Will Have: Contribute to the development of cutting-edge technologies that drive the Era of Smart Everything. Enhance the performance and reliability of next-generation semiconductor IPs. Accelerate the time-to-market for high-performance silicon chips. Reduce risks associated with layout design by adhering to stringent verification requirements. Foster a collaborative and innovative work environment. Support Synopsys mission to lead in chip design and software security. What You'll Need: BTech/MTech in Electrical Engineering or related field. 2+ years of relevant experience in analog layout design. Proficiency in developing quality layouts and performing physical verifications. In-depth understanding of deep submicron effects and floorplan techniques. Experience with CMOS, FinFET, and GAA process technologies at 7nm and below. Knowledge of layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.

Working on challenging technical problems in the verification domain under the Synopsys Verification Platform. Engaging with HDL/HVL methodologies and dynamic simulation aspects, including debugging. Collaborating with global teams to propose and implement solutions. Utilizing your knowledge of UNIX, Tcl, and other scripting languages to enhance productivity. Participating in continuous learning and staying updated with the latest verification technologies. Contributing to a diverse environment and interacting with domain experts across various locations. The Impact You Will Have: Accelerating the design and verification of high-performance silicon chips. Enhancing the usability and adoption of Synopsys verification products and solutions. Optimizing chip designs for power, cost, and performance, thereby reducing project schedules. Driving technological innovation and contributing to the development of next-generation processes and models. Fostering collaboration and knowledge sharing within a global team. Supporting the creation of advanced technologies that power self-driving cars, AI, the cloud, 5G, and IoT. What You'll Need: Bachelor's degree in Electronics with 3+ years experience or a Master's degree in Electronics with 2+ years experience. Proficiency in verification technologies such as Simulation, UVM, SVA, and LRM. Experience with Synopsys EDA tools (e.g., VCS, Verdi) is an advantage. Strong fundamentals in digital design, HDLs (Verilog/VHDL), and System Verilog. Excellent written and oral communication skills for effective global team interactions.

Conceptualizing, designing, and productizing state-of-the-art circuit components for SLM monitors realized through ASIC design flow. Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. Developing statistical simulation methodologies and collaborating with the layout team to achieve optimal design solutions. Characterizing designed custom cells and deploying new circuits into test chips for post-silicon characterization. Creating new cells and updating existing ones through collaboration with architects and Physical Design engineers. Conducting pre and post-layout simulations and characterizations across various design corners to ensure reliability and aging requirements. The Impact You Will Have: Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages. Enhancing the reliability and differentiation of products in the market with reduced risk. Driving innovation in custom circuit design methodologies and tools. Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You'll Need: BS or MS degree in Electrical Engineering with 5+ years of relevant industry experience. Strong custom design experience, including specification, circuit design description, and schematics. Proficiency with circuit design and simulation tools, IC design CAD packages from any EDA vendor. Sound understanding of SPICE simulator concepts and simulation methods. Experience with statistical design methodologies like generating and analyzing Monte-Carlo results.

Contribute to modeling, integration, and testing of various peripherals in SystemC-based platform modeling framework Understand IP modeling requirements and generate ESL model specifications Resolve technical issues related to IP modeling and platform integration Guide junior engineers and consultants on SoC platform creation and validation Support software bring-up and debug platform integration issues Collaborate with cross-functional teams to ensure successful execution and delivery The Impact You Will Have: Advance platform modeling and integration of high-performance silicon chips Improve efficiency and scalability of SystemC-based frameworks across domains like Automotive and Wireless Ensure accurate and functional SoC platform creation and validation Provide mentorship and technical leadership to junior engineers Deliver high-quality modeling solutions that align with Synopsys innovation goals Enable successful deployment of next-gen technologies through robust platform models What You'll Need: Bachelor's or Master's in Electrical Engineering or Computer Science 6+ years of industry experience Strong proficiency in C++, SystemC/TLM modeling Solid understanding of bus/memory architectures and SoC interfaces Familiarity with protocols such as IEEE 802.3 Ethernet, PCIe (preferred) Experience in modeling SoC peripherals using C++/SystemC/HDL (preferred) Knowledge of AMBA, AXI, OCP, or NoC protocols (preferred) Exposure to assembly or high-level application development and multicore platforms (preferred)

What You'll Be Doing: Designing and implementing SOC solutions for various applications, ensuring high performance and reliability. Collaborating with cross-functional teams to define and develop SOC architecture and specifications. Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements. Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives. Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies. Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation. Job Description and Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors. Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC. Understand the design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure that the design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer. Required B.E/B. Tech/M.E/M. Tech in electronics with 4-9 years experience in RTL Design and Verification. Hands-on experience on static verification tools such as Spyglass performing LINT, CDC, RDC. Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossing. Good conceptual understanding of RTL rule checks. Hands-on experience on synthesis and timing constraints development. Candidates with experience on ARM based technologies (Coresight Debug, Processor architecture, etc.) will be preferred.

Take ownership and drive on-time delivery of patches and releases for small products. Assist other Release Managers on larger products and assignments. Independently drive commitments and convergence of patches and releases as per established processes, welcoming new ideas. Act as the interface between R&D, DevOps, management, and Application Engineers. Utilize excellent interpersonal, communication, and follow-up skills to ensure team collaboration and success. Apply hands-on experience in C/C++ software development to enhance project outcomes. What You'll Need: Hands-on experience in C/C++ software development. In-depth knowledge of program management concepts. Experience with Perforce, Perl, Shell scripts, Python, Make, and other industry-standard configuration management tools. Proficiency in Unix environments. 5+ years of relevant experience in program management, process and releases, or software development. Excellent academic background with a B.E./B.Tech/M.Tech in Computer Science, Electrical, or Electronic Engineering from reputed universities.

Category Engineering Hire Type Employee Job ID 9622 Remote Eligible No Date Posted 25/03/2025 Formal Verification Principal Engineer: We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced Formal Verification Specialist with a strong background in RTL design and a passion for ensuring the correctness and reliability of digital designs. You have a minimum of 10+ years of industry experience, with at least the last 5 years focused on formal techniques for verification. You possess deep knowledge of architectures of designs and digital logic, synthesis flow, static timing flows, and formal checking. Your hands-on experience with HDLs such as Verilog or System Verilog and understanding of temporal logic assertions make you an ideal candidate for this role. You have worked on complex verification projects and have experience with formal verification tools like Jasper or VC-Formal. Your skills in Python, Perl, or Shell scripting are a plus. You are a team player with excellent communication skills, capable of mentoring junior engineers and collaborating with geographically diverse cross-functional teams. Your problem-solving abilities and attention to detail enable you to debug RTL designs effectively and identify causes of failure scenarios. You hold a Bachelor's or Master's degree in Computer Science or Electrical Engineering from a reputed engineering college. What You'll Be Doing: * Specifying, implementing, and maintaining an integrated end-to-end formal verification flow for the formal verification objective. * Guiding and training team members on effective usage of FV tools. * Reviewing formal setups and proofs with design and verification teams. * Maintaining and extending assertion libraries, including support for both simulation and formal verification. * Identifying key behaviors for verification of DUT and creating a formal verification plan. * Developing verification environments, including environment assumptions, assertions, and cover properties in the context of the verification plan. * Applying various formal verification techniques to prove the correctness of digital designs. * Debugging RTL to identify causes of failure scenarios. The Impact You Will Have: * Enhance the reliability and quality of our digital designs through rigorous formal verification. * Contribute to the development of high-performance silicon chips and software content. * Improve the overall design and verification process by maintaining and extending assertion libraries. * Facilitate knowledge sharing and skill development within the team by providing guidance and training on FV tools. * Ensure the correctness of designs by identifying key behaviors and creating comprehensive verification plans. * Support the success of geographically diverse cross-functional teams through effective collaboration and communication. What You'll Need: * Strong knowledge of architectures of designs and digital logic. * Experience with synthesis flow and static timing flows, formal checking, etc. * Hands-on experience with HDLs such as Verilog / System Verilog. * Understanding of temporal logic assertions. * Experience with at least one formal verification tool (e.g., Jasper, VC-Formal). * Experience with complex verification projects that used formal techniques for closure. * Skills in Python, Perl, or Shell scripting (a plus). Who You Are: * A seasoned professional with a comprehensive understanding of formal verification techniques. * A collaborative team player with excellent communication skills. * A problem solver with strong debugging skills. * A mentor capable of guiding junior engineers and interns. * An individual with a proactive and detail-oriented approach to work. The Team You'll Be A Part Of: You will be part of the Solutions Group at our Bangalore Design Center, India. This team focuses on delivering high-quality digital designs and verification solutions. The position offers learning and growth opportunities, allowing you to work with a diverse group of talented engineers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned VLSI professional with extensive experience in product engineering management. Your background includes at least eight years of hands-on experience in VLSI product engineering, with a deep understanding of analog and digital SOC design flows. You have a proven track record of working on various technology nodes and driving product innovation. Your expertise spans across RTL Development, RTL Verification, and RTL to GDS flow, making you a versatile asset to any team. You excel in customer-centric roles, adept at managing multiple projects and setting priorities effectively. Your communication skills, both written and verbal, are top-notch, and you have a knack for interfacing with different levels of an organization. You are well-versed in database management and maintaining data cleanliness across product portfolios. If you are looking for a new challenge and are passionate about driving product success in the VLSI domain, we would love to connect with you. What You'll Be Doing: Collaborating with cross-functional teams to drive product success. Developing and executing product engineering strategies. Serving as the technical interface between teams. Interacting with Sales and Pre-Sales teams. Buildingtimeplansand schedules for product development. Ensuring customer satisfaction by addressing and prioritizing issues effectively. The Impact You Will Have: Driving the success of our VLSI products through strategic engineering management. Enhancing product innovation by working on various technology nodes. Improving customer satisfaction through effective communication and issue resolution. Ensuring seamless technical interfacing between cross-functional teams. Contributing to the development of high-performance silicon chips and software content. Supporting the sales process by providing technical insights and solutions. What You'll Need: Minimum 5 years of experience in VLSI product engineering. Exposure to analog and digital SOC design flows and methodologies. Experience in RTL Development, RTL Verification, and RTL to GDS flow. Proven track record of working on different technology nodes. Ability to manage multiple projects and set priorities effectively. Who You Are: Customer-centric with excellent communication skills. Able to interface with different levels of an organization. Proficient in database management and maintaining data cleanliness. Experienced in buildingtimeplansand schedules. Knowledgeable about industry trends and emerging technologies in VLSI. The Team You'll BeAPart Of: You will be part of a dynamic and innovative project management team dedicated to driving product success in the VLSI domain. Our team collaborates closely with cross-functional teams, including Sales, Pre-Sales, and technical experts, to ensure the successful development and delivery of high-performance silicon chips and software content. We are passionate about continuous technological innovation and strive to create a collaborative and supportive work environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In this Role, you will be accountable for: Design and development of Transistor level analog and mixed signal layout. Device level floorplan, placement, routing, and physical verification. Troubleshoot Physical verification issues to get clean and desired results. In charge of creating and reviewing layout documents to ensure they meet quality standards and are delivered on time. Job Requirements: Candidate must have a bachelor's or master's degree and a minimum 5 years of experience in Analog and Mixed Signal Circuit Layout. Experience in Analog Layout Flow from Device placement till GDS release. Should be able to do planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Sound knowledge in Electrical and Electronic fundamentals. Solid Knowledge in Semiconductor device physics, good knowledge of CMOS, FINFET technologies. Knowledge of CMOS Fabrication technology and deep sub-micron effects and its impact on layout. Must know the Electro migration and other Reliability Concepts, ESD/LUP concepts and apply to layout. Hands on knowledge in EDA tools for Custom Mixed signal layout flows. Passionate to learn and explore new techniques. Must be self-directed, detail oriented with good problem-solving skills and communication skills. Effectively communicating with cross-functional team for successful project execution. Experience in Tcl is a plus . At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share

Category Engineering Hire Type Employee Job ID 10209 Remote Eligible No Date Posted 30/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background inPhysicaldesign,physicalverificationand STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments andpossessa passion for creating innovative technology. Yourexpertiselies in working with advancedFinfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of ourcutting-edgetechnology products. WhatYou'llBe Doing: * Conceptualizing, designing, and productizingstate-of-the-artRTLto GDS implementationfor SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * DevelopingDigital BE activities includessynthesis, pre-layout STA,SDCconstraints development, floor planning, bump placement, power planning, MV design techniques,VCLP, UPFunderstanding,placement, CTS, routingand collaborating with thedifferent functionalteamsto achieveoptimaldesign solutions. *Post layout STA,timing& functionalECOdevelopment, timingsignoffmethodologyat higher frequency IPdesignsclosure. * Physical verification, DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff. * Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams. * Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. *Optimizingperformance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation inPhysical design, physical verification, STA and signoffdesign methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. WhatYou'llNeed: * BS/B.Techor MS/M.Techdegree in Electrical Engineering with 5+ years of relevant industry experience. * StrongPhysical design, physical verification,pre&post layoutSTA andEMIR/Powersignoffexperience, includingSDCdevelopment, UPF/Mutlivoltagedesigndevelopment experience. * Experience in DRC, LVS, DFM cleaning andtimingclosureis mandatory. * Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/VCLP/PT/PT-PX/ICV and Redhawk * Sound understanding of Physical design, Physical verification and STA and signoff concepts. * Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providingphysical design and signoffsolutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10094 Remote Eligible No Date Posted 01/04/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: We are seeking innovative and out-of-the-box thinking Design For Test (DFT) Engineers to be a part of the Fast Solution Team under the Test Group at Synopsys. You are someone who thrives in a project-oriented environment, delivering comprehensive DFT solutions ranging from integration to silicon bring-up for customers designing digital ICs of varying complexity. You excel in assessing customer methodologies and flows, gathering requirements, and proposing solutions. You are adept at providing technical support to ensure customer success and satisfaction, winning new customers through product demonstrations, evaluations, and competitive benchmarking. You are skilled in resolving technical problems, training, and account management, and you can interact effectively with end-users at customer sites and with first-level managers. You are also responsible for working with Solution Architects to develop and productize the next-gen test technologies. Your role involves prototyping new methodologies, analyzing gathered data, identifying the viability of technology, and presenting the findings under the guidance of a Solution Architect. What You'll Be Doing: Providing expertise for test solutions during design planning, budgeting, and implementation. MBIST implementation and validation, including BIST architecture planning, memory grouping, pattern generation, validation, silicon bring-up, diagnostics analysis, and debug. Participating in customer's design and flow reviews. Driving, prototyping, and developing new Design for Test methodologies. Multitasking across various issues and priorities to help customers exploit new technologies. Collaborating with Solution Architects to develop and productize next-gen test technologies. The Impact You Will Have: Enhancing Synopsys ability to deliver cutting-edge test solutions that meet customer needs. Contributing to the successful integration and silicon bring-up of complex digital ICs. Ensuring high customer satisfaction through effective technical support and problem resolution. Driving innovation in test methodologies and technologies. Supporting the development of next-gen test technologies that push the boundaries of what's possible. Playing a key role in winning new customers and expanding Synopsys market presence. What You'll Need: Minimum BS+10 years of relevant experience/MS+8 years of relevant experience in Electrical Engineering, Computer Engineering, or other relevant fields of study. Experience with RTL coding, DFT insertion, ATPG, MBIST architecture planning, insertion, validation, pattern generation, and silicon bring-up. Excellent knowledge of memory BIST flows, memory fault models, MBIST algorithms, hard/soft repair, and eFuse repair flow. Experience in handling memory BIST for large, complex SoCs with various IPs. Exposure to MBIST of automotive designs is a plus. Good understanding of protocols like 1149.1, 1500, 1687. Who You Are: You possess excellent soft skills and can communicate effectively with various stakeholders. You are highly motivated, proactive, and can work independently with limited supervision. Your advanced knowledge and wide-ranging experience enable you to work on complex issues requiring in-depth evaluation of various factors. You are a sophisticated professional who can communicate and influence parties within and outside your subfamily area. The Team You'll Be A Part Of: The Test Group at Synopsys is a critical part of the change, delivering a complete DFT solution to fulfill customer needs. You will be part of the Fast Solution Team, working closely with Solution Architects and other engineers to develop and productize next-gen test technologies. This team is dedicated to driving innovation and ensuring customer success through comprehensive test solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share