Job
Description
As a skilled professional with a Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience, along with 6 years of expertise in ARM-based System on a chip (SoCs), interconnects, and Application-Specific Integrated Circuit (ASIC) methodology, you are well-equipped to take on the responsibilities of this role. Additionally, your 5 years of experience in Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture, coupled with your proficiency in a coding language like Python or Perl, make you an ideal candidate for this position. Ideally, you hold a Master's degree or a PhD in Electrical Engineering, Computer Science, or possess equivalent practical experience. Your 6 years of industry exposure in Intellectual Property (IP) design, familiarity with methodologies for RTL quality checks such as Lint, CDC, RDC, and expertise in low power estimation, timing closure, and synthesis further enhance your qualifications for this role. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in innovating products that are cherished by millions worldwide. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration. In this role, you will be responsible for designing foundation and chassis IPs (such as Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU), and other peripherals) for Pixel System on a chip (SoCs). Collaborating with cross-functional teams including architecture, software, verification, power, timing, and synthesis, you will be involved in specifying and delivering high-quality Register-Transfer Level (RTL). Your role will entail solving technical challenges related to micro-architecture, low power design methodology, and evaluating design options while considering performance, power, and area requirements. Google's mission to organize the world's information and make it universally accessible and useful is at the core of our work. By combining the best of Google AI, Software, and Hardware, we strive to create remarkably helpful experiences for our users. Our team is dedicated to researching, designing, and developing cutting-edge technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to improve people's lives through technology. Key Responsibilities: - Participate in test planning and coverage analysis. - Develop Register-Transfer Level (RTL) implementations aligning with power, performance, and area objectives. - Engage in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA) and silicon bring-up processes. - Conduct Verilog/SystemVerilog RTL coding, functional and performance simulation debugging, and Lint/CDC/FV/UPF checks. - Create tools and scripts to automate tasks and monitor progress effectively.,
