3 Verilogsystem Verilog Jobs

As a skilled professional with a Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience, along with 6 years of expertise in ARM-based System on a chip (SoCs), interconnects, and Application-Specific Integrated Circuit (ASIC) methodology, you are well-equipped to take on the responsibilities of this role. Additionally, your 5 years of experience in Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture, coupled with your proficiency in a coding language like Python or Perl, make you an ideal candidate for this position. Ideally, you hold a Master's degree or a PhD in Electrical Engineering, Computer Science, or possess equivalent practical experience. Your 6 years of industry exposure in Intellectual Property (IP) design, familiarity with methodologies for RTL quality checks such as Lint, CDC, RDC, and expertise in low power estimation, timing closure, and synthesis further enhance your qualifications for this role. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in innovating products that are cherished by millions worldwide. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration. In this role, you will be responsible for designing foundation and chassis IPs (such as Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU), and other peripherals) for Pixel System on a chip (SoCs). Collaborating with cross-functional teams including architecture, software, verification, power, timing, and synthesis, you will be involved in specifying and delivering high-quality Register-Transfer Level (RTL). Your role will entail solving technical challenges related to micro-architecture, low power design methodology, and evaluating design options while considering performance, power, and area requirements. Google's mission to organize the world's information and make it universally accessible and useful is at the core of our work. By combining the best of Google AI, Software, and Hardware, we strive to create remarkably helpful experiences for our users. Our team is dedicated to researching, designing, and developing cutting-edge technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to improve people's lives through technology. Key Responsibilities: - Participate in test planning and coverage analysis. - Develop Register-Transfer Level (RTL) implementations aligning with power, performance, and area objectives. - Engage in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA) and silicon bring-up processes. - Conduct Verilog/SystemVerilog RTL coding, functional and performance simulation debugging, and Lint/CDC/FV/UPF checks. - Create tools and scripts to automate tasks and monitor progress effectively.,

About The Team Finance Governance is a team within Group Finance The strong, multi-cultural team environment within the team provides an environment to succeed Team members have a direct influence on how we operate and are encouraged to bring and develop new insights and solutions Being part of the Group Finance, staffed globally, will give you experience of a truly multi-national, multi-cultural environment You will also have opportunity to see the larger picture of Swiss Re as a multi-national company, About The Role Do you like inspiring change and enabling risk insights through powerful analyticsThen you are best placed to apply for this position The team's directive is to use its technical and analytical capabilities to steer the identification, quantification and mitigation of the Division and groups' operating risks through digitisation This is a position where one can actively apply their technical expertise and help the team progress on its directive, while also building functional expertise in governance and Finance operations, You will be part of the Enablement and Integration team within Financial Governance, collaborating closely with financial governance experts, collaborating closely in functional and technical domains The team focuses on developing scalable data solutions and tools to support Financial governance operations and analysis, This role involves working together very closely with our dedicated global governance teams across Bangalore, Bratislava, and Zurich, Key Responsibilities Include Supporting the entire Finance Governance team by applying your technological and analytical skills Strongly contribute to develop and drive Financial Governance's overall digitisation strategy in automated controls and IT audits Working with your colleagues from across the globe to identify focused control areas and conceptualise pre-emptive and digital controls; you will then take a leading role in automating/digitising those controls and prepare necessary documentation Evaluating the team's current manual and semi-manual controls to develop automation capabilities/solutions Taking the ownership on specific projects, relevant to Finance Governance's digitisation efforts Own Governance-specific applications, tools, etc Your can-do demeanour will help you and the team further improve processes by applying smart approaches and implementing technical solutions, About You Bachelors in a quantitative field, e-g Applied Mathematics, Engineering, Physics, Computer Science, Finance or similar Those with data science or master's degree would be preferred Minimum 5 years of analytical experience in data analytics, business intelligence or similar role Certification / Expertise in advanced analytics tools not limited to SQL, R, Python, Machine Learning and, or data integration platforms e-g Palantir Foundry Strong knowledge on visualisation tools mainly PowerBI Ability to work across the organisation to understand an identified risk area and then developing/implementing a concise solution to quantify and mitigate the risk Support the development of the Financial Governance data model and associated reporting Contribute to GenAI/LLM use cases in Financial Governance using Palantir Foundry (Stargate), Maintain and improve existing Financial Governance tools and applications, Design and build robust data pipelines in Palantir Foundry (ETL layer), working with structured and semi-structured data, Develop logic to enrich, align, and transform data from multiple source systems into integrated data models, Drive and own development of dashboards and automation tools (Power BI, PowerApps, Power Automate), Perform data quality checks and support ongoing change management, Actively contribute to simplifying the data & tools landscape by identifying automation opportunities, Review existing Stargate analytic capabilities and applications to (i) support in optimising the performance and (ii) provide feedback and coaching to team members on best practices Translate functional needs into clear, actionable data requirements and technical specifications Perform other ad-hoc tasks as required from time to time A positive and independent personality who enjoys taking ownership and not shy to expand your own role/portfolio Ability to work on your own initiative and implement solutions Good communication and social skills Ability to work in a multi-cultural and multi-location environment Fluency in English is required About Swiss Re Swiss Re is one of the worlds leading providers of reinsurance, insurance and other forms of insurance-based risk transfer, working to make the world more resilient We anticipate and manage a wide variety of risks, from natural catastrophes and climate change to cybercrime We cover both Property & Casualty and Life & Health Combining experience with creative thinking and cutting-edge expertise, we create new opportunities and solutions for our clients This is possible thanks to the collaboration of more than 14,000 employees across the world, Our success depends on our ability to build an inclusive culture encouraging fresh perspectives and innovative thinking We embrace a workplace where everyone has equal opportunities to thrive and develop professionally regardless of their age, gender, race, ethnicity, gender identity and/or expression, sexual orientation, physical or mental ability, skillset, thought or other characteristics In our inclusive and flexible environment everyone can bring their authentic selves to work and their passion for sustainability, If you are an experienced professional returning to the workforce after a career break, we encourage you to apply for open positions that match your skills and experience, Keywords Reference Code: 135054

The company Advantal Technologies is currently looking to fill multiple positions at their Bengaluru client site, including Embedded Engineers, FPGA Engineers, Technical Leads, and Testers. They are seeking individuals with varying levels of experience ranging from 3 to 7 years for most positions, with a minimum of 8 years of experience required for the Technical Lead role. For the Embedded Engineer position, candidates should have experience in C programming on Bare Metal, development on Xilinx MPSoC (preferably ZCU 106/104), hands-on experience on Xilinx Vitis, and familiarity with protocols such as I2C, SGMII, UART, and SPI. Desirable skills include knowledge of MISRA C coding guidelines, DO-178C, and device driver development. Experience in security aspects like authentication, certificates, and encryption/decryption is also valued. The FPGA Engineer role requires experience in RTL coding using Verilog, development on Xilinx MPSoC (preferably ZCU 106/104), hands-on experience on Xilinx Vivado and Vitis, and familiarity with Microblaze. Desirable skills include knowledge of MISRA C coding guidelines, DO-254, and security aspects similar to the Embedded Engineer position. For the Technical Lead position, candidates should have a minimum of 8 years of experience and at least 2 years of experience leading teams. They should possess a strong understanding of embedded system development, real-time application development, bare-metal code development using C, FPGA design flow, and digital design development using Verilog HDL. Additionally, experience in DO-178C compliance, software development using API, networking protocols, and security aspects like authentication, authorization, and encryption is required. Testers are required to have a minimum of 3 years of experience in testing embedded systems, test case design, execution, and familiarity with Zynq Ultrascale MPSoC, Xilinx Vivado, Verilog/System Verilog, QuestaSim, and code coverage. If you are interested in any of these positions, please reach out to hr@advantal.net for further information.,