ASIC Engineer, IP Design

You will be a part of a team that focuses on developing custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation behind widely loved products worldwide. Your role will involve designing foundation and chassis IPs for Pixel System on a Chip (SoCs) and collaborating with various teams to deliver high-quality Register-Transfer Level (RTL) designs. As a key member of the team, you will solve technical challenges related to micro-architecture, low power design, and evaluate design options considering performance, power, and area constraints. - Work collaboratively with the team to deliver coherent fabric interconnect solutions. - Define microarchitecture details such as interface protocol, block diagram, data flow, and pipelines. - Engage in RTL development using SystemVerilog, debug functional/performance simulations. - Conduct RTL quality checks including Lint, CDC, Synthesis, and UPF checks. - Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up processes. - Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience. - 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture. - 5 years of experience with ARM-based System on a Chip (SoCs), interconnects, and Application-Specific Integrated Circuit (ASIC) methodology. - Experience with a coding language like Python or Perl. Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience. - 6 years of industry experience with Intellectual Property (IP) design. - Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC). - Experience with methodologies for low power estimation, timing closure, synthesis.,