Senior RTL Design Engineer-Barcelona

Role Overview: You will be part of the RTL team and will work on various aspects of a RISC-V design for an advanced technology node. Your primary focus areas will include the processor pipeline, d-cache, i-cache, the l2-pipeline, and a custom memory controller. As a vertical engineer, you are expected to possess a strong RTL or architecture/microarchitecture background and be capable of understanding and solving complex problems at the RTL level. Key Responsibilities: - Work on multiple areas of a RISC-V design, including the processor pipeline, d-cache, i-cache, the l2-pipeline, and a custom memory controller - Collaborate with the team to ensure efficient RTL design and implementation - Utilize your knowledge of Verilog to develop and optimize RTL code - Participate in the design and verification of various components within the RISC-V design Qualifications Required: - Bachelor's degree in computer science - Minimum of 8 years of experience in a similar role - Proficiency in Verilog - Strong scripting skills (Note: No additional details about the company were provided in the job description.),