Formal Verification Lead (SMTS)

As a Formal Verification Engineer at AMD, you will play a crucial role in the Advance Formal Verification team, dedicated to providing formal functional and security verification for a variety of IPs. Your expertise in IP verification, formal verification methodologies, and high-speed IO bus protocols will be instrumental in ensuring the highest level of design quality through cutting-edge formal verification technologies. Your responsibilities will include collaborating with architects and designers to understand design intents, creating and executing formal verification plans, writing and debugging properties for design verification, optimizing runtime using formal techniques, and reporting status and progress. For senior positions, you will lead and coordinate verification activities for a small team, train junior engineers, develop working procedures, flows, and infrastructure, and handle complex formal problems. The preferred experience for this role includes 12+ years of combined ASIC/FPGA design and verification experience, expertise in formal property verification, sequential equivalence checking, and academic formal methods. You should be well-versed in formal property languages, abstraction techniques, formal sign-off, and commercial formal tools, with extensive experience in verifying complex designs and high-speed protocols. Familiarity with industry-standard protocols such as PCIe, SATA, USB, and AXI, as well as hardware-firmware interaction verification, is highly desirable. To qualify for this position, you should hold a BS (or higher) degree in Electronics/Electrical or Computer Engineering. This role is based in Bangalore, India, offering an opportunity to contribute to AMD's mission of building great products that accelerate next-generation computing experiences. Join AMD's transformative journey and be part of a team that pushes the limits of innovation to solve the world's most important challenges. Together, we advance the future of technology.,