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Senior Staff Engineer SOC DV

Senior Staff Engineer SOC DV

8 - 10 years

|

6 - 10 Lacs

Posted:21 hours ago| Platform:

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Skills Required

Usage formal verification ISO SOC Analytical Perl System verilog UVM functional safety Python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Required Qualifications

System Verilog, UVM, C
Scripting languages (Python, Tcl, Perl)
Understanding of bus protocols (AXI, AHB, APB, etc.)
Proven written and verbal technical communication skills
Ability to collaborate in a team environment
Excellent analytical and problem-solving skills.
Experience 8- 10 years

Preferred Qualifications

From-scratch development of IP or SoC testbenches
Familiarity with RISC-V architecture, Functional Safety Standards (ISO 26262)
Background with power-ware (UPF) and gate-level simulations (GLS)
Ownership of complete verification cycle (verification planning -> coverage closure) in a project
Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements
Knowledge of UVM Register Abstraction Layer (RAL) and integration of 3rd party VIPs

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