330 Soc Design Jobs - Page 4

As a Master's degree student in Electronics and Communication Engineering or a related field, you will be joining our team for a full-time internship lasting approximately 11-12 months. Your main focus will be on SoC design, working closely with our experienced design team to develop cutting-edge hardware for specific applications such as Automotive, IoT, voice/object recognition, security, smart connectivity, and touch sensing. - Collaborate with the design team to create state-of-the-art SoC hardware for various applications - Assist in the end-to-end ownership of SoC Design, Verification, and implementation - Design and verify digital and Mixed-signal IPs - Document designs and present re...

Role Overview: As a Hardware Engineer at Qualcomm, you will be responsible for the Logic design, micro-architecture, and RTL coding of complex SoCs. Your expertise will be crucial in ensuring the successful design and integration of SoCs, as well as collaborating with verification and validation teams for pre/post Silicon debug. Key Responsibilities: - Hands-on experience with SoC design and integration - Proficiency in Verilog/System-Verilog - Knowledge of AMBA protocols such as AXI, AHB, and APB - Understanding of SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC - Familiarity with Memory controller designs and microprocessors - Experience in constraint deve...

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow's future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in Chiplet Ar...

Design and implement synthesis flows using Synopsys Design Compiler. Collaborate with cross-functional teams to alignmethodologywith design requirements. Drive innovation in SoC design methodologies, tools, and flows. Provide technical leadership and support to resolve RTL, DFT, and synthesis-related issues. Interface with EDA vendors to evaluate and integrate new tool features. Ensuremethodologyscalability and robustness across multiple projects. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSI Design. 5–8 years of hands-on experience with...

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse...

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you w...

About The Job Role Choosing Capgemini means choosing a place where youll be empowered to shape your career, supported by a collaborative global community, and inspired to reimagine whats possible.Join us in helping leading Consumer Products and Retail Services (CPRS) organizations unlock the value of technology and drive scalable, sustainable growth. Your Role: As a System Power, Thermal and Performance Engineer , you will play a critical role in validating and optimizing system-level performance across CPU, GPU, and AI/ML workloads. Youll work on Android and Linux platforms, leveraging your understanding of SoC subsystems and performance/power KPIs to drive efficiency and innovation. In thi...

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilitie...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

Role Overview: You will be responsible for complex SOC Top Physical Implementation for next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. This will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Conduct top-level floor planning including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs, and optimize Power, Performance, and Area (PPA)....

Role & responsibilities: Familiarity with NIST 800-61 or SANS IR cycle Containment techniques (isolate endpoint, disable account, block IP/domain). Evidence handling & chain of custody. Root cause analysis and post-incident reporting Core Technical Skills: Security Monitoring & SIEM Expertise Proficiency in tools like Splunk, QRadar, Sentinel, ArcSight, Elastic SIEM. Writing correlation rules, dashboards, and alerts. Incident Detection & Triage Identifying false positives vs. real incidents. Prioritizing based on risk/impact. Threat Hunting & Analysis Using indicators of compromise (IoCs), TTPs, MITRE ATT&CK mapping. Proactive search for hidden threats. Endpoint & Network Forensics EDR tools...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

Looking for suitable engineers with 4+ years of experience in SOC, Block Level P&R activities Must have worked in at least 1 Full Chip tape outs. Must be hands-on technical expert. Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling) Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all stages of the design (IO Pad-ring, Power Planning, floor planning, placement, CTS, Routing, noise reduction/crosstalk, extraction, IR drop, LVS/DRC and other physical and electrical checks) Experience in Low power and high-perform...

You have a rewarding opportunity at Qualcomm India Private Limited in the Engineering Group, specifically in the Hardware Engineering team. As a Senior SoC Design Engineer, you will play a crucial role with your extensive experience in SoC design and expertise in various protocols and architectures. Let's delve deeper into the responsibilities and qualifications required for this role: **Role Overview:** - Utilize your 15+ years of experience in SoC design to contribute effectively to the team - Demonstrate proficiency in AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking/reset/debug architecture - Showcase your knowledge of peripherals like USB, PCIE, and SDCC - Gain an under...

System-on-Chip Design Lead Engineer Job Title: Front End SOC Lead /Architect / PE Location: Bangalore, India Experience level: 10+Years Role - 10+ Years of relevant industry experience in multiple SoC designs. Strong technical background in driving SoC design independently. Experience in low power architecture definition. Well versed with Performance analysis Experience in processor system integration, NoC design and integration, Good understanding of high-speed protocols such as PCIe/DDR/HBM/Ethernet etc.. Defining sign-off quality design constraints for SoC. Hands-on expertise with low-power design techniques such as UPF/CPF. Hand-on experience in system modeling. Good to have Mixed Signal...

Role & responsibilities Preferred candidate profile Digital Design Engineer Technical Skills • Must-Have: • Proven experience in RTL coding and RTL integration of sub-blocks into larger components • Strong expertise in RTL linting debug and error/warning fixes using VcSpyglass • Deep knowledge in analyzing and resolving CDC/RDC violations using Questa • Solid understanding of clocking and reset concepts, including synchronization, generation, and division • Nice-to-Have: • Familiarity with memory subsystems, Tensilica DSP cores and/or communication/control peripheral bus systems • Understanding of on-chip interconnect structures such as Arteris FlexNoC and AMBA protocols • Basic knowledge of...

Test Automation Lead: Domain Knowledge: Familiarity with video/image processing pipelines (H.264/H.265 codecs, MIPI sensors, Ethernet video output). Understanding of FPGA/SoC architectures, especially RISC-V-based SoCs. Data Extraction of FFMpEG Knowledge of Linux-based embedded environments. Automation Development: Strong in Python scripting for test automation - pytest, paramiko, pexpect, etc. Ability to design test frameworks for CLI-driven systems Experience in automating regression, stress, and reboot test cases. Verification Tools & Assets: Hands-on with Git, Jira, Confluence for versioning and tracking Exposure to video quality validation Selected candidate will be working on test aut...

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse...

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MI...

Role Overview: As a SOC Architect/Lead at SvelteTech, you will play a crucial role in designing, implementing, and leading the next-generation Security Operations Center. You will have the opportunity to make a significant impact by utilizing your expertise in SOC design, Elastic Stack, SIEM/SOAR, and leading security teams. Key Responsibilities: - Architect and implement SOC using tools such as Elastic SIEM, SOAR, and threat intel pipelines - Lead and mentor SOC Engineers to build dashboards, detection logic, and correlation rules - Drive proactive threat hunting and integrate global intel sources like MISP, OTX, and AbuseIPDB - Establish IR workflows, escalation paths, and ensure complianc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

About The Role Your Role As a SoC GLS Verification Engineer , you will play a key role in verifying complex SoC designs through Gate-Level Simulation (GLS). You will work closely with design and verification teams to ensure functional correctness, timing accuracy, and overall quality of silicon-ready designs. Your expertise in GLS methodologies and debugging will be critical in delivering high-performance, reliable SoCs. In this role, you will: Perform GLS using Zero Delay , SDF , and Post-Layout GLS (PAGLS) techniques. Debug and resolve issues in gate-level simulations to ensure timing and functional correctness. Develop and maintain SystemVerilog/UVM testbenches for GLS environments. Colla...