1691 Physical Design Jobs - Page 4

We are looking for a skilled Senior Manager - Physical Design with 10-15 years of experience to lead our team in Bangalore, Hyderabad, Noida, Coimbatore. The ideal candidate will have a strong background in physical design and excellent leadership skills. Roles and Responsibility Manage and lead a team of physical design engineers to achieve project goals. Develop and implement automation scripts for physical design methodologies. Collaborate with front-end engineers to resolve timing and power issues. Evaluate new tools and drive power reduction of designs. Perform floorplanning and time budgeting for successful project execution. Ensure timely completion of projects by managing resources e...

Job details: Job Title: Digital RTL Design Engineer Location: On-Site Experience Level: Mid-Senior (3-7 years) Job Description: Responsibilities: Design and implement digital RTL for complex systems. Collaborate with verification engineers to ensure design meets all functional and performance requirements. Perform synthesis, timing analysis, and optimization to meet design specifications. Debug and resolve design issues, ensuring high-quality and reliable designs. Participate in design reviews and provide constructive feedback. Document design processes, specifications, and methodologies. Work closely with cross-functional teams (DFT, PD, DV) for integration and sign-off. Requirements: Bache...

Build your career with Sykatiya Technologies. Sykatiya Technologies values technical ability and the attitude of its highly talented team, which is reflected in the contributions to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. Role Overview: - Lead a team in the development of at least 1 IO library from specification to GDS. - Possess good knowledge of all collateral views, their quality assurance, and the ability to review collaterals. - Guide the layout team on design constraints and conduct layout reviews. - Experience working on FinFET nodes with a strong understanding of...

Job Description Join SanDisk India as a Technical ASIC Project Leader and take charge of developing cutting-edge ASICs that power the next generation of SD cards for imaging, gaming, mobile, and data storage. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities: Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisk s storage solutions...

About the Role: We are seeking a highly experienced and motivated Principal Engineer specialising in SoC RTL Design for System-on-Chip (SoC) solutions. As a key technical skill, you will drive the SoC Architecture, Design, and integration of complex digital systems , collaborating with cross-functional teams to deliver next-generation semiconductor products. Key Responsibilities: Define and review SoC architecture and design specifications . Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog. Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab . Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical...

Job Description Position Overview: We are seeking a highly skilled and experienced Principal Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities: - Own complete STA signoff for ASIC, providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP & Design team for Timing constraints Develop...

Job Description We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 9-14 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely w...

Role Overview: As a Physical Design Engineer at UST, you will be expected to have a strong understanding of the Basic Fundamentals of C-MOS technology and a comprehensive knowledge of the PD Flow for flat and hierarchical designs. Your responsibilities will include independently handling RTL/Netlist to GDSII conversions at block level/SS/SoC and executing multiple tape outs with a focus on low power implementation. Experience in floor planning, partitioning, integration at Subsystem/Chip, and hands-on exposure to lower technology nodes such as 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm, etc., will be crucial. You will also be involved in floor planning, placement optimizations, clock tree synthes...

Alternate Job Titles: R&D Staff Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a motivated and forward-thinking engineering professional eager to make a meaningful impact in the semiconductor industry You thrive in collaborative environments and are passionate about solving complex technical challenges Your exper...

Alternate Job Titles: R&D Staff Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a motivated and forward-thinking engineering professional eager to make a meaningful impact in the semiconductor industry You thrive in collaborative environments and are passionate about solving complex technical challenges Your exper...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world s most important challenges striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

We are looking for a hardworking and dedicated member to join the SOC Power Algorithms and Software Features team in the AMD Client Computing and Graphics group. Power architects guide SoCs from early concept stages through design execution and post silicon. This role involves collaboration with many teams across including SoC architecture definition, IP design, integration/physical design, platform architecture, software, firmware, packaging, and silicon validation. Contributions have a direct impact on the power & performance of AMD s Client products. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings,...

SYMPHISYS SOFTWARE CONSULTING is looking for ASIC Physical Design Engineer to join our dynamic team and embark on a rewarding career journey Collaborate with cross-functional teams to achieve strategic outcomes Apply subject expertise to support operations, planning, and decision-making Utilize tools, analytics, or platforms relevant to the job domain Ensure compliance with policies while improving efficiency and outcomes Disclaimer: This job description has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying.

Backup and recovery processes and tools Database knowledge (logical and physical design) Experience with troubleshooting database performance issues and query tuning concepts Perform data management tasks as required: loading / unloading, updating, restoring and removing data to ensure that database is accurate as a data source. Perform Database Maintenance activities like Adhoc Reorgs, Runstats etc on demand from the application teams, as well as monitor the scheduled maintenance activities. Monitor and manage Space: Purge obsolete data and reclaim space Identify and troubleshoot databases issues with high priority. Monitor database backups and Database maintenance jobs. Troubleshoot job fa...

ROLES & RESPONSIBILITIES • Will be responsible for all aspects of Physical Design for Full chip/Blocks covering Floor planning, Placement, Clock Tree planning & analysis, Routing ,Timing Budgeting. Signoff STA closure with SI analysis

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on own...

Overview: We are looking for a highly motivated and detail-oriented Block-Level Physical Design Engineer to join our dynamic VLSI team. You will be responsible for driving the complete physical implementation of complex digital blocks using industry-standard tools and methodologies, targeting advanced technology nodes including 7nm/5nm and beyond. Key Responsibilities: Execute block-level physical design activities including Floor planning, Placement, Clock Tree Synthesis (CTS), Routing , and Physical Verification . Perform Static Timing Analysis (STA) , IR drop analysis, RC extraction , and ensure power, timing, and signal integrity closure. Work hands-on with tools like Cadence Innovus , S...

Job Description Hand-on experience and Comprehensive knowledge of Static Timing Analysis. Hands-on experience in Logical aware Synthesis, Logical Equivalence check and, Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge in the Timing closure on Sub-system level & Block level and Chip level. Knowledge in writing Manual ECOs to fix timing violations and DRCs. Knowledge of constraint development. Good Knowledge of TCL scripting and UNIX env. Leading the team of 4 to 5 team members by guiding and mentoring on the STA /Synthesis. Pre-layout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closu...

We are looking for a skilled professional with 5-15 years of experience to join our team as an SCOM in IDESLABS PRIVATE LIMITED, located in [location to be specified]. The ideal candidate will have a strong background in recruitment services and excellent communication skills. Roles and Responsibility Manage and coordinate recruitment activities to meet client requirements. Develop and implement effective recruitment strategies to attract top talent. Build and maintain relationships with clients and candidates for successful placements. Conduct interviews and assessments to identify the best candidates. Collaborate with internal teams to ensure seamless recruitment processes. Analyze recruit...

Deep understanding of Circuit design/ physical design of Analog Designs on advanced process technologies Expertise in analogy design of blocks like Analog to Digital converters, Amplifiers, Switch-cap circuits, Voltage, and Current Reference Generation circuits, GPIO, Differential Tx / Rx, oscillators, ESD, etc Expertise in Reliability aware design and familiarity with Aging and RV tools. > Ability to design floor plan and routing in Layout Good grasp of Industry-standard tools such as Cadence design Environment (ADEXL or Virtuoso) Knowledge of DRC, LVS, and post-layout extraction tools, etc Familiarity with RTL behavioral coding and simulations, timing extractions of custom blocks Strong co...

Experience doing physical design targeted to the 7nm/16nm FinFet process Good knowledge of cell libraries various views and models Good understanding of static timing analysis (STA), EM/IR, and sign-off Strong hands-on experience with Chip Level / Sub-chip level floor planning, > partition, pin assignment, Power planning, Bump Planning, Pad Ring Creation, > Block level physical implementation, timing closure, physical verification, Chip level integration of different sub-blocks, and custom macros/IPs, Timing, IR/EM analysis and closure, Physical Verification - block and chip level EDA Tool Expertise: Innovus, Tempus/PrimeTime-SI, Voltus/RedHawk, StarXT/Quantus, Calibre,LEC, etc Good software...

Good understanding of timing concepts, a good understanding of SDC and constraints syntax, and experience in Timing Analysis both at block level and SoC level. You must have experience with Industry Timing sign off tools like Prime time / Tempus, DMSA or Tweaker, and MMMC As a Static Timing Analysis Engineer, you will work with the design and implementation teams to develop and qualify timing constraints, solve timing challenges in Block/SOC by manually closing difficult paths, and work closely with the physical design engineers to resolve implementation-related timing issues. You should also have a clear understanding of Cross-talk delay/noise, Timing derates, AOCV/POCV concepts, and its im...

Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/ Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementatio n (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 20+ years Hardware Engineering experience or related work experience. 17+ years experience with PNR flo...

THE PERSON: You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems. KEY RESPONSIBILITIES: Lead floor-planning, placement, routing, custom clock tree design, and optimization. Expert knowledge and hands-on experience of the entire backend and adjacent flows, including synthesis, Floor-planning P&R, clocking, timing closure, power and IO planning Perform all aspects of de...

The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMDs next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies...