432 Physical Design Jobs - Page 4

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects.. Job Description. In your new role you will:. Implement high-performance, low-power, and area-efficient digital designs.. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis.. Optimize designs for power, performance, and area, and meet PPA goals.. Power analysis using PT-PX or equivalent flow.. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs.. Define and evaluate constraints and signoff Test/DFT mode timing requirements.. Your Profile. You are best equipped for this task if you have:. Strong fundamentals and experience in Synthesis and STA domains.. Write and implement block level and top-level timing constraints for Synthesis. Optimize designs for power, performance, and area, and meet design goals.. Knowledge on Power analysis and PT-PX flow.. Understanding of DFT flows, including scan insertion.. Write and evaluate Test/DFT mode timing constraints.. Thorough with Logic Equivalence Check debug capability.. Well known about UPF concepts and Low Power Checks at block and full chip level.. Defining and verification of STA constraint for Functional and Test/SCAN Modes.. Defining PVT’s corners required for covering all desired scenarios for a design. Knowledge on OCV/AOCV/POCV derates.. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues.. VASTA timing closure based on chip IR drop.. Knowledge on signal SI analysis and PT-PX flow.. Contact:. swati.gupta@infineon.com. #WeAreIn for driving decarbonization and digitalization.. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.. Are you in?. We are on a journey to create the best Infineon for everyone.. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills.. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.. Click here for more information about Diversity & Inclusion at Infineon.. Show more Show less

Requisition #: 16978 Our Mission: Powering Innovation That Drives Human Advancement When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys. Innovate With Ansys, Power Your Career. Summary / Role Purpose As a Product Specialist II , you will be part of the team responsible for overall development and validation of Ansys EDA Products. This involves working with Software developers, Architects, Application Engineers, and Semiconductor Customers, from ideation all the way to final product release and deployment. Key focus areas will include all areas related to IP/SoC/3DIC Power Integrity, Signal Integrity, Reliability aspects like EM/ESD/Thermal, Advanced timing/jitter, Packaging - the top challenges for any chip design on advanced nodes like 7/5/3 nm. Key Duties and Responsibilities Be part of Product Engineering Team that Works with Global-Customers / IP-providers / Foundries to understand design challenges of cutting-edge SoCs & 3DICs on 7/5/3 nm and creates EDA product specifications. Works with Software developers to develop state-of-the-art EDA products solving Power-Noise-Reliability challenges across Chip-Package-System Works on Ansys-Seascape platform - Semiconductor Industry s First and Only True Big-Data design Platform! Performs in-depth validation to ensure Product meets accuracy and other requirements. Collaborates with Application Engineers to support Global Customers in solving their design challenges on leading edge SoCs. Minimum Education/Certification Requirements and Experience Bachelor s/Master s degree in Electronics Engineering/VLSI from Top Institutions (NITs/IITs and likes) Strong problem-solving skills Good programming skills Excellent verbal and written communication skills Preferred Qualifications and Skills Passion to learn and deploy new technologies. Ability for minimal travel 2-3 years of prior experience in either of a) ASIC Physical design, b) Power-Integrity / Signal-Integrity / Reliability Closure c) Custom circuit design and simulation At Ansys, we know that changing the world takes vision, skill, and each other. We fuel new ideas, build relationships, and help each other realize our greatest potential. We are ONE Ansys. We operate on three key components: our commitments to stakeholders, our values that guide how we work together, and our actions to deliver results. As ONE Ansys, we are powering innovation that drives human advancement Our Commitments: Amaze with innovative products and solutions Make our customers incredibly successful Act with integrity Ensure employees thrive and shareholders prosper Our Values: Adaptability: Be open, welcome what s next Courage: Be courageous, move forward passionately Generosity: Be generous, share, listen, serve Authenticity: Be you, make us stronger Our Actions: We commit to audacious goals We work seamlessly as a team We demonstrate mastery We deliver outstanding results VALUES IN ACTION Ansys is committed to powering the people who power human advancement. We believe in creating and nurturing a workplace that supports and welcomes people of all backgrounds; encouraging them to bring their talents and experience to a workplace where they are valued and can thrive. Our culture is grounded in our four core values of adaptability, courage, generosity, and authenticity. Through our behaviors and actions, these values foster higher team performance and greater innovation for our customers. We re proud to offer programs, available to all employees, to further impact innovation and business outcomes, such as employee networks and learning communities that inform solutions for our globally minded customer base. WELCOME WHAT S NEXT IN YOUR CAREER AT ANSYS At Ansys, you will find yourself among the sharpest minds and most visionary leaders across the globe. Collectively, we strive to change the world with innovative technology and transformational solutions. With a prestigious reputation in working with well-known, world-class companies, standards at Ansys are high met by those willing to rise to the occasion and meet those challenges head on. Our team is passionate about pushing the limits of world-class simulation technology, empowering our customers to turn their design concepts into successful, innovative products faster and at a lower cost. Ready to feel inspired? Check out some of our recent customer stories, here and here . At Ansys, it s about the learning, the discovery, and the collaboration. It s about the what s next as much as the mission accomplished. And it s about the melding of disciplined intellect with strategic direction and results that have, can, and do impact real people in real ways. All this is forged within a working environment built on respect, autonomy, and ethics. CREATING A PLACE WE RE PROUD TO BE Ansys is an S&P 500 company and a member of the NASDAQ-100. We are proud to have been recognized for the following more recent awards, although our list goes on: Newsweek s Most Loved Workplace globally and in the U.S., Gold Stevie Award Winner, America s Most Responsible Companies, Fast Company World Changing Ideas, Great Place to Work Certified (China, Greece, France, India, Japan, Korea, Spain, Sweden, Taiwan, and U.K.). For more information, please visit us at www.ansys.com Ansys is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other protected characteristics. Ansys does not accept unsolicited referrals for vacancies, and any unsolicited referral will become the property of Ansys. Upon hire, no fee will be owed to the agency, person, or entity.

Overview About Business Unit: A consolidated team of database technology professionals, we provide expertise across all major database engines and Big Data solutions to support Epsilon products and platforms. The team has a unique alignment that combines a horizontal organizational structure with vertically aligned sub-groups dedicated to our clients. By adhering to consistent standards and best practices, the team ensures operational excellence and has close ties with product teams at Oracle, IBM, Cloudera, Amazon and Microsoft. Why we are looking for you: At Epsilon, we deliver excellence and create connections that last a lifetime. Our digital marketing arm, Conversant, is now growing and we are on the lookout for dedicated individuals who believe that every interaction counts - and want to make an impact on the future of our clients businesses. So, are you someone who wants to work on the cutting edge of new-generation UI technology? Does the thought of working with Data Warehouse, Machine Learning, and Artificial Intelligence excite you? Then you could be exactly who we re looking for. Apply today and be part of a dynamic, enthusiastic and passionate team who want nothing more but to make a lasting impact on the lives of consumers. You will also get the opportunity to see your ideas come to life on almost every consumer device across the US. What you will enjoy in this role: Seeking a highly motivated and well-rounded Senior Oracle DBA with a strong development background to be part of a fast-paced production support and full-lifecycle implementation team. Candidate is expected to be familiar with database architecture, logical and physical design, automation, documentation, installs, shell scripting, PL/SQL programming, backup & recovery concepts, and database performance and tuning. Candidate must have good analytical, verbal, and written skills. Click here to view how Epsilon transforms marketing with 1 View, 1 Vision and 1 Voice. Responsibilities What you will do? Full life cycle support of clients database(s). Database system applies RAC and non-RAC for OLTP and warehouse, Active DataGuard for DR, partitioning on 12c and 19c on premises and cloud environment. Oracle Exadata patching and maintenance experience is a must. Responsible for database backups, design, development, testing, and performance tuning. Will work with developers to design and build new structures to support application enhancements and promote database changes throughout the Dev, UAT and Prod databases. Responsible for quarterly patch applications (PSU) and periodic database upgrades with minimal downtime in database environment. Required to participate in 24x7 on-call rotation and be available to perform periodic after-hours support. Proactively think toward automation of repeated tasks. Qualifications 6+ years of related experience with implementation and administration of database systems. Bachelor Degree or equivalent experience required. Able to administer, manage and tune high-transaction Standalone/RAC production server environment(s) on premises and cloud environments. Able to understand and meet needs of end users. Able to work with multiple projects in a dynamic, fast paced and often changing environment. Strong design, development, administration skills. Strong knowledge on managing Automatic storage management. Strong analytical abilities to solve complex database performance issues using AWR/ASH/ADDM/TKPROF/SQLT/10046 tracing/OSWatcher/CHM etc. Strong knowledge on Oracle Exadata Strong knowledge of database upgrade/migrations. Strong knowledge in using Backup and recovery tools(RMAN/EXPDP/IMPDP) Strong knowledge of Oracle DataGuard Physical Standby configuration, build and support including DataGuard Broker and replication. Knowledge on database programming and query troubleshooting. Knowledge on Oracle Enterprise Manager. Experience in managing Database in AWS cloud environment. Experience in writing Shell scripts. Have good written/oral communication and soft skills. Oracle certification can be plus. Additional Information Epsilon is a global data, technology and services company that powers the marketing and advertising ecosystem. For decades, we ve provided marketers from the world s leading brands the data, technology and services they need to engage consumers with 1 View, 1 Vision and 1 Voice. 1 View of their universe of potential buyers. 1 Vision for engaging each individual. And 1 Voice to harmonize engagement across paid, owned and earned channels. Epsilon s comprehensive portfolio of capabilities across our suite of digital media, messaging and loyalty solutions bridge the divide between marketing and advertising technology.

Principal DFT Engineer (MBIST) in Pune, MH, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. What youll achieve: DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist Boundary Scan insertion, simulation and verification Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis Scan ATPG pattern generation, simulation and debug on RTL and gates netlist Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data Bachelors degree & 8 years of related experience or Masters degree & 6 years of related experience Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses. Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions. Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions. Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features. Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development. Experience in working with physical design teams to support STA constraints, reviewing timing reports. Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue. Experience in setting up and running Scan DRC flows in RTL. Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl. Experience in revision control systems like GIT, perforce etc.. Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug. Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Principal DFT Engineer (MBIST) in Bangalore, KA, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. What youll achieve: DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist Boundary Scan insertion, simulation and verification Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis Scan ATPG pattern generation, simulation and debug on RTL and gates netlist Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data Bachelors degree & 8 years of related experience or Masters degree & 6 years of related experience Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses. Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions. Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions. Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features. Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development. Experience in working with physical design teams to support STA constraints, reviewing timing reports. Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue. Experience in setting up and running Scan DRC flows in RTL. Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl. Experience in revision control systems like GIT, perforce etc.. Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug. Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Physical Design Full Chip Low Power verification 10+ yrs

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. At Arm, our work goes beyond multiple divisions where we'drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience : Bachelors or masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh. Nice To Have Skills and Experience : Knowledge around Arm based CPUs and SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding! Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience : Bachelors or masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh. Nice To Have Skills and Experience : Knowledge around Arm based CPUs and SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises

Working experience in Physical Design implementation areas including Synthesis, LEC, and PnR as we'll as good exposure to signoff areas, particularly power, timing, and IR signoff. Job Description Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification , and taking blocks to the closure. Design Application Engineering (DAE ) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point of contact for project teams in case of issues and will work to achieve the highest customer interaction. Responsible for automation of manual processes (including design flow/design package qualification mechanisms, generation of test reports/dashboards etc) and providing automation requirements for reducing manual steps in qualification. The candidate will have an internal drive to work with design and EDA vendors to solve issues and adopt new flows. The candidate should have reasonable ability to automate design work by means of script programming, eg Tcl/tk, Perl or Python. Your Profile The candidate should have a minimum of 6 years of relevant working experience in Physical Design implementation areas including Synthesis, LEC, and PnR as we'll as good exposure to signoff areas, particularly power, timing, and IR signoff. One should have a deep understanding of and be able to be cater to design concerns across semi-custom design flows, including RTL analysis, synthesis, LEC, Place and Route, STA, EM/IR, and physical verification. One should be able to identify flow gaps and provide automation on need base to perform all design activities in the most efficient and correct-by-construction way. One should be able to evaluate solutions from multiple available options and be able to perform trade-offs between technical features. Analyse the results and any inconsistency issues to be reports via bug tracking system. One will work with R&D in Infineon globally and EDA tool vendors to resolve issues across semi-custom design flows. One will coordinate with IT and EDA tool license teams to provide an infrastructure aligned with project needs. One should have exposure to basic version management using any of Clearcase / Perforce / Cliosoft / Git. You should possess excellent communication skills to interact effectively with peers and customers in a clear and honest manner with consistent and open to learning new technical areas if the need arises. You should define and monitor key test metrics, build regression status reporting dashboard, Develop and execute QA test plans, verification methodology & test strategies for digital block/chip level to maximize the coverage of features/methodology supported in the technologies/Design Flows.

As a member of the AECG ASIC Group, you will help bring to life cutting-edge designs. As a member of the Back-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA we'll versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring full chip level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure P REFERRED EXPERIENCE : 12+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Successfully led static timing analysis (STA) and closure for 2 3 SoC projects from RTL to tape-out. Proficient in analyzing SoC architecture to derive appropriate timing constraints and define STA methodology. Skilled in translating architectural and design specifications into accurate timing constraints (SDC), including clock definitions, generated clocks, exceptions (false paths, multi-cycle paths), and hierarchical timing. Coordinated cross-functional efforts across design, synthesis, P&R, and verification teams to ensure timing signoff. Owned timing budgets, constraint development, and timing ECOs, achieving first-pass silicon success. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams. Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Experience in working full-chip STA closure, defining mode requirements and corners for timing closure. Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: we'll versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring block/SS level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: 3+ years of experience for timing closure of block/SS Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. Good understanding of SDC construct ( clock generation , false path , multi cycle paths..) ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

We are looking for Physical Design Engineers with Exp in Low Power Verification with above 10yrs Exp

Plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Collaborate with cross-functional teams to develop solutions and meet performance requirements. Hands-on Physical Design (PD) execution at block/SoC level with a focus on Power, Performance, Area (PPA) improvements. Strong understanding of technology and PD Flow Methodology enablement. Work with Physical Design engineers to roll out robust methodologies, identify areas for flow improvement (area/power/performance/convergence), develop plans, and deploy/support them. Provide tool support and issue debugging services to physical design team engineers across various sites. Develop and maintain 3rd party tool integration and productivity enhancement routines. Understand advanced technology Place & Route (PNR) and Static Timing Analysis (STA) concepts and methodologies, and work closely with EDA vendors to deploy solutions. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Skill Set: Strong programming experience & Proficiency in Python/Tcl/C++. Understanding of physical design flows using Innovus/fc/icc2 tools. Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory. Basic understanding of Timing/Formal verification/Physical verification/extraction are desired. Ability to ramp-up in new areas, be a good team player, and excellent communication skills desired. Experience: 3-5 years of experience with the Place-and-route and timing closure and power analysis environment is required.

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Role: SOC level Mixed Signal and High Speed Interfaces verification Engineer Experience: 1 to 6 years in Design Verification Responsibilities: Responsible for RTL and GLS level validation at SOC. Post Silicon validation support. Required Skills and Knowledge: Familiarity with basic concepts of SV, UVM, and C-based test case bring-up. Understanding of GLS simulations and debug is a plus. Good in communication. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Specs : We are seeking a highly skilled and motivated ASIC Physical Design Experts to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Design IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location and Expertise: Bangalore : 4 Years 15 Years Beijing : 8 Years 10 Years Chennai : 3 Years 6 Years Vietnam : 8 Years 10 Years Taiwan : 8 Years 10 Years Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C / VLSI with 3+ Years of work expertise in ASIC Physical Design Expertise in managing, mentoring and training team of ASIC physical design engineers working across different time zones, this is mandatory for lead positions Expertise in ASIC PD. Expertise in digital physical design Expertise in working with 3nm & 5nm technology nodes Expertise in EDA synthesis, APR, STA tools and methodologies Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk Expertise in working with multi modes and multi corners STA Working Knowledge of multiple power planes and multiple VT libraries Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification Good at scripting languages PERL, TCL, shell Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs Expertise in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization Expertise in making ECOs both Metal and logic level ecos Expertise in DRC and LVS cleanup of designs during sign off Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit.

As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success. THE PERSON: A successful candidate will work on block level and SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work with PD team on subsystem and block level physical verification and signoff Work closely with physical design implementation and signoff team to achieve faster TAT Work closely with CAD team to come up with new flows and methodologies in the physical verification domain PREFERRED SKILLSET: 3+ years of relevant experience Sound knowledge of physical verification and design flows Hands on experience on industry standard tools such as Calibre and ICV Sound understanding for DRC/LVS decks. Should be able to make updates as required. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Front-End Silicon Design & Integration (FEINT) Engineer The role: A Front-End Silicon Design and Integration (FEINT) Engineering role in our Security IP (SECIP) team, where a large number of embedded micro-processor subsystems, hardware accelerators and other IPs vital to improve system performance and functionality are designed and verified. These IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, perform ECO and LEC checks, as well as support SOC integration of the IPs. The person: A talented FEINT engineer with strong records of technical ownership and execution to drive synthesis, PPA analysis, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities: Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result) Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies Develop, adopt and automate RTL static design rule checks in collaboration with Back-End Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team Develop and adopt FEINT design and verification infrastructure, methodology and tools Preferred experience: BSc with a minimum of 5 years relevant experience, or MSc with a minimum of 3 years Proven understanding of RTL design, synthesis, and ECO principles Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, etc. Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile) Excellent skills with Unix/Linux environment Familiar with RTL coding techniques for competitive PPA-measured QoR Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.) Good understanding of gate level circuit design and physical level design concept and methodology Familiar with VCS/Verdi and SPG based (dynamic/static) verification environments Excellent communication skills (both written and oral) Self motivated, and committed to achievement Academic credentials: Bachelors Degree or Masters Degree in Electrical Engineering, Computer Engineering, or possibly a related field Masters Degree preferred #LI-PS1 Benefits offered are described: AMD benefits at a glance .

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com . Job Description The position involves design verification of next generation modem sub systems (which has MAC, Baseband and RF IP s involved for latest Wi-Fi protocol including 11ax) with emphasis on verifying and signing off performance and power along with functionality. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS and Formal techniques. Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. He/She will work with design team (both HW and SW) on RTL debug during Pre-silicon HW development phase. Responsibilities: Develop and execute verification plans using SystemVerilog and UVM to validate complex ASIC/FPGA designs. Design and implement testbenches and verification environments to ensure functional accuracy and performance. Perform Gate-Level Simulations (GLS) to validate designs against their RTL implementations. Create and run comprehensive verification scenarios and identify discrepancies between RTL and gate-level simulations. Collaborate with design engineers to understand requirements and resolve design issues. Debug and troubleshoot complex issues, providing detailed analysis and solutions. Document verification processes, methodologies, and results to ensure clarity and reproducibility. Participate in design reviews and contribute to improving verification strategies and methodologies. Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Collaborate with cross-functional teams to define and execute gate-level simulation test plans. Develop and implement gate-level simulation strategies for complex digital designs. Conduct gate-level simulations to verify the functionality and performance of digital designs. Work closely with design and verification teams to identify and resolve issues at the gate level. Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process. Ensure compliance with industry standards and best practices in gate-level simulation. Develop a comprehensive GLS methodology for the CPU Perform gate-level simulations to verify the functionality, performance, and timing of CPU designs. Develop and execute comprehensive test plans for gate-level simulations. Collaborate with RTL design, verification, and physical design teams to identify and resolve simulation issues. Analyze simulation results, debug failures, and propose design improvements. Ensure thorough coverage and validation of all critical paths and corner cases. Automate simulation workflows to enhance efficiency and reproducibility. Assist in the development and maintenance of simulation environments and tools. Document simulation methodologies, results, and best practices. Understanding of industry-standard protocols and interfaces Familiarity with static timing analysis (STA) and power analysis. Understanding of power domains and HW programming guide sequences Develop test plan to verify all low power states Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Exploring innovative dynamic or static methodologies by engaging with EDA vendors Experience Level: 6-8 years in Industry Education Requirements: Bachelor or Master s degree in Electrical and/or Computer Engineering Minimum Qualifications: 6-8+ years of professional experience in ASIC/FPGA verification with strong expertise in SystemVerilog, UVM, and Gate-Level Simulation (GLS). Proven experience in developing and executing testbenches and verification environments. Strong skills in performing gate-level simulations and analyzing results. Excellent debugging skills with the ability to resolve complex design issues. Effective communication and collaboration skills, capable of working well in a team environment. Analytical debugging skills Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Low-power implementation (UPF) Mixed Signal Real Number Modeling (RNM, Spice) Strong System Verilog/UVM based verification skills Experience with Assertion coverage-based verification methodology Experience in formal / static verification methodologies will be a plus Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Experience with Synopsys NLP (native Low Power) tool. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Proficiency in Low-Power standards like UPF/CPF. Working knowledge on UPF based RTL / PGPIN simulations. Proficiency in ASIC design tools, simulation methodologies, and hardware description languages (HDLs). Excellent analytical and problem-solving skills with a focus on power optimization Preferred Qualifications: Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

Job Responsibilities : Process & quality monitoring for respective technology plants Identify and analyse deviations Perform root cause analysis Propose corrective action and track the status of process improvement Identify opportunities for profit improvement Identify opportunities for product quality enhancement Process design calculations for the improvement schemes Develop process design package using appropriate tools Participate in commercial plant trials Understand and evaluate basic engineering design documents Participate in plant performance audits as per set guidelines Participate in Critical PHAs and turnaround activities of the related plants Validate MoCs to ensure specified standards and codes are followed in calculations Support preparation of stage gate-2 and 3 document for Capital projects Participate in HAZOP of new projects Validate equipment data sheets prepared by engineering contractor Contribute to derive value from technology network Education Requirement : BE/B Tech in Chemical Engineering from a reputed institute Experience Requirement : 4 years of experience with at least 2 years in plant Operations / CTS Skills & Competencies : Analytical ability for problem solving Programming exposure Knowledge of chemical engineering and process technology Ability to plan / discuss results and network under the guidance of a senior colleagues Process design calculations at Skill level Use of process calculation templates at Skill level Simulation skills Use of Six sigma for problem solving Good communication skills Leadership quality with management skills Result Orientation

With this position you will be in our Technical Ladder: a special career path for those who share innovative ideas, demonstrate comprehensive technical knowledge, show thought leadership, possess problem solving abilities and are able to create business value, Job Description In your new role you will: Contribute to highly complex designs in a multi-site organization covering all aspects of Structural and Physical SoC Design Be responsible for the physical design of multifarious digital SoCs Translate requirements into layout specifics using our state-of-the-art EDA tools and flows Work independently in different phases of the RTL2GDS flow: With focus on (one or many) Synthesis and equivalence check, generation of Floorplans, Placement, Clock Trees, Routing and Power Distribution Network for efficient Timing Closure with Signal Integrity and physical Sign off including Power Integrity Take physical limitation of hierarchical deep sub-micron designs into account and timely implement suitable solutions to overcome implementation issues, Tap your experience to contribute s Your Profile You are best equipped for this task if you have: A degree in Electrical Engineering, Microelectronics or a similar field At least 3-5 years of working experience in Physical Design of highly complex SoCs with sound experience in Synthesis, Place & Route and Timing Closure and involvement in FINFET technologies Know-how in technical leadership in physical design projects Sound programming skills and knowledge in scripting languages like Tcl, Perl or Python Basic experience in RTL coding Understanding of Functional Safety will be a benefit Fluent English language skills with German being an added plus Contact: Gowri Shenoy, LinkedIn #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals Be a part of making life easier, safer and greener, Are you in We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities We base our recruiting decisions on the applicant?s experience and skills, Please let your recruiter know if they need to pay special attention to something in ord

Job Responsibilities : Education Requirement : Experience Requirement : Skills & Competencies : Work Output Define project charters and implementation plan, Develop project proposal for management approval & budget Manage projects within allocated budget & resources available, Coordinate with key stakeholders at sites for implementation & embedding of the new process/system, Coordinate with partner/vendor for project execution Actively contribute in managing Knowledge Assets, Evaluate information gathered through workshops & surveys and incorporate in process description, Identify the competitive commercial solution for recommendation, Communicate with internal teams & external clients to deliver functional requirements like GUI, screen, and interface designs, Review process automation documents Plan & schedule end user trainings, Address/resolve application related issues faced by customers, Translate usability and field implementation findings into design improvement Other: Stay updated with the latest automation technologies Analyse & provide necessary up gradation / modification plan to existing automation systems, Co-development with the vendor, technology providers Audit of existing automation facilities and processes, Data Management Collect and analyse data for automation systems, Standardization of reports / templates, Customized reports, Create SOPs/other documents HSE & Other Regulatory Compliance: Carry out risk assessment studies prior to implementation, Follow and enforce applicable HSE procedures/practices Display awareness and compliance of site, statutory, IP and RIL IT regulations Min BE/B Tech in Chemical Engineering from a reputed institute Min 4 years of experience with at least 2 years in plant Operations / CTS Should have aptitude/flair for working with automation systems Analytical ability for problem solving and programming exposure, Flair to learn new technologies, Good awareness of P&ID, PFD, Instrumentation and control systems Good knowledge of at least 1-2 unit operations / processes, Good communication skills Leadership quality with management skills Result Orientation Business Process driven outlook Knowledge of office automation packages

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 3-10 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

DFT Implementation: Strong expertise in implementing DFT architectures, including Scan Insertion, ATPG (Automatic Test Pattern Generation), and MBIST/ LBIST for SoC designs. Test Coverage Optimization: Experience in optimizing test coverage while minimizing test cost and pattern volume. Scan & Compression Techniques: Proficient in scan chain design, scan compression techniques, and reducing test data volume. Boundary Scan (IEEE 1149.1): In-depth knowledge of boundary scan standards and Fault Models: Familiarity with various fault models (stuck-at, transition, path delay, etc.) and their application in test generation. DFT Tools: Hands-on experience with DFT tools like Synopsys TetraMAX, Mentor Graphics Tessent, Cadence Modus, etc. Scripting & Automation: Proficiency in scripting languages (e.g., Perl, Python, TCL) for Sign-Off: Experience with DFT sign-off procedures, including coverage analysis, vector generation, and fault simulation. Post-Silicon Validation: Knowledge of silicon bring-up, ATE (Automatic Test Equipment), and post-silicon validation techniques. Expectations from the Role: Technical Expertise: Demonstrated expertise in DFT methodologies, with the ability to implement robust DFT solutions across complex SoC designs. Problem-Solving: Strong analytical and problem-solving skills, particularly in diagnosing and resolving DFT-related issues. Collaboration: Effective communication and teamwork skills, with the ability to work closely with RTL designers, verification teams, and physical design teams. Innovation: Ability to innovate and improve existing DFT methodologies, driving advancements in test coverage and efficiency. Attention to Detail: High attention to detail, ensuring that all test structures are correctly Project Management: Ability to manage multiple projects, prioritize tasks effectively, and ensure timely delivery of high-quality DFT solutions.

Physical Design Implementation: Experience in block and SoC level PD implementation, covering the entire flow from netlist to GDSII, including PnR/APR. Low Power Design: Proficient in low power design techniques. Flow Expertise: Hands-on experience with floorplanning, power planning, placement, CTS (Clock Tree Synthesis), routing, extraction, and DFM (Design for Analysis Skills: Strong ability to perform congestion and timing analysis, with a focus on achieving better QoR (Quality of Results). Sign-Off Expertise: In-depth knowledge of sign-off processes including STA (Static Timing Analysis), DRC/LVS/Antenna/ERC checks, power analysis, IR/EM analysis, LEC (Logic Equivalence Checking), and ECO (Engineering Change Order) for both Process Knowledge: Comprehensive understanding of the entire physical design process from RTL to GDSII, encompassing floorplanning, placement, CTS, routing, and sign-off stages. ECO Implementation: Experience in implementing ECOs. PnR Tools: Hands-on experience with PnR tools such as Synopsys ICC II and Scripting Skills: Proficient in scripting languages like Perl and TCL, with experience using various EDA tools. Expectations from the Role: Debugging & Problem-Solving: Excellent debugging and problem-solving skills, with the ability to tackle complex design issues. Communication: Effective communication skills for interacting with all Focus & Commitment: Must be highly focused and committed to achieving project goals and closing out tasks. Independence: Ability to work independently and manage tasks with minimal Leadership: Possesses strong leadership skills with a proactive, go-getter attitude.

BSEE and at least 5 years of prior experience are required. MSEE and at least 3 years of previous experience are strongly preferred. Prior experience in timing and or RTL design of high-speed interfaces. Prior experience collaborating with Physical Design teams in multiple successful ASIC/IP Tape Outs. Knowledge of the IP/SoC level timing closure flow and methodology. Strong command of Verilog/System Verilog language. Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies. Ability to handle multiple projects/tasks successfully. Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow. Hands-on experience in timing constraints generation and management. Proficiency in scripting languages (TCL and Perl). Familiarity with synthesis, logic equivalence, DFT and backend-related methodology and tools. Capability to understand and implement improvements to existing methodologies and flows. Strong background in Constraint analysis and debugging, using industry-standard tools. Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, at speed and Best testing. Team player with a passion for innovating and a can-do attitude. Self-starter and highly motivated. Desired Skills : Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs. Experience designing or integrating IP. Experience in high-speed and low-power digital design using advanced deep-micron processes. Experience with highly configurable designs