Radiant Semiconductors is a leading Semiconductor Design and Services Company with a strong presence across India and the USA. Backed by 200+ skilled engineers, over 7 years of industry relevant experience, were specialised in Design Verification, Design For Test (DFT), PD and Analog Design. We deliver tailored solutions through flexible engagement models, serving top Semiconductor Companies worldwide by our leadership team with 18+ years of expertise in product development. Role: Junior DFT Engineer Location : Bengaluru, Candidate should be flexible to work PAN India Eligibility Criteria Qualification : B.E/ B.Tech, M.Tech/M.E (Will get preference) Stream : Electronics Engineering or Related Fields Post Graduation Year : 2024 or Prior (Up to 2020) Academic Requirement : Minimum 65% throughout academics Background : Strong foundation in VLSI Design, Digital Electronics, Scan & DFT Fundamentals What we offer Competitive Salary Package aligned with Industry Standards Comprehensive Family Health Insurance Coverage Opportunity to work on high-impact semiconductor projects with top-tier global clients Professional training with the focus on industry standard EDA tools Opportunity to continuous learning and mentorship support from Industry experts Employee Recognition: Get acknowledged and rewarded for innovation, performance, and dedication Selection Process Online Registration Written Test (Shortlisted Candidates) Technical Interview (Selected Candidates) HR Discussion & Final Offer Important Dates Last Date to Application- 14th June Written test (Shortlisted Candidate )- 27th June Technical Interview (Selected Candidates)- 28th June HR Discussion & Final Offer- 28th June Click on the link to Apply now and become a part of Radiants Dynamic DFT team: https://forms.gle/ZCNcACE9Eigx5iuq6
About Radiant Semiconductors Radiant Semiconductors is a leading VLSI services firm specializing in Design Verification, Physical Design, Design For Testability, Analog Layout & Analog Circuit Design for global clients. We are committed to delivering high-quality semiconductor solutions while fostering a collaborative and innovative work environment. As we are expanding we are looking for an experienced Design Verification Engineer to contribute to cutting-edge semiconductor projects Job Description 12 to 25 Yrs of experience in ASIC/SOC/IP Verification plan definition, test bench environment development in System Verilog/UVM Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level Support of assertion and coverage-driven methodology Develop test cases to verify functional operation of that the system level Experience in any of the protocol like AMBA or AHB or USB or SPI2 or PCIe or NVMe or UFS or SATA or SAS or Ethernet or AXI or DDR Communicate test progress, test results, and other relevant information to project lead Analyze formal test results in order to discover and report any defects, bugs, errors, configuration issues, and interoperability. Code and functional coverage objects of different block What We Offer Competitive salary package and benefits Opportunity to Work with top tier clients on cutting-edge semiconductor projects Collaborative and innovation-driven work environment Career growth and mentorship opportunities Show more Show less
Radiant Semiconductors is a global player in Semiconductor Industry Founded in 2018, offering tailored semiconductor solutions to meet clients' needs, Headquarters in Bengaluru, Hyderabad and USA. Our services are RTL Design, ASIC Verification, Physical Design, DFT, Analog Layout, Analog Design and Physical Verification. Our dedicated and experienced team of engineers ensures delivery of high-quality results to accelerate clients' success. Trust in Radiant to illuminate your path to success. Why Radiant? 🌟 Competitive Salary & Benefits 📈 Career Growth Opportunities 🤝 Collaborative Work Environment 🎯 Cutting-Edge Projects We have Job Opportunity for Analog Layout Engineer Experience – 3 to 8 Yrs Location – Noida Availability – Immediate to 15 Days Job Description Design and implement analog layouts for high-performance circuits (e.g., amplifiers, ADCS, DACS, voltage regulators) using TSMC/Samsung 7nm and below nodes. Perform design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC) to ensure design compliance. Required Skills: Strong experience in analog layout design at advanced nodes (TSMC/Samsung 7nm and below). Proficiency in layout tools like Cadence Virtuoso, Synopsys IC Compiler, or similar. Understanding of layout-dependent effects (LDE) and its impact on performance. Knowledge of parasitic extraction, simulation, and optimization. Familiarity with design for manufacturability (DFM) techniques. Knowledge on Basic SKILL/PERL. Show more Show less
About Radiant Semiconductor Radiant Semiconductors is a global player in Semiconductor Industry Founded in 2018, offering tailored semiconductor solutions to meet clients' needs, Headquarters in Bengaluru, Hyderabad and USA. Our services are RTL Design, ASIC Verification, Physical Design, DFT, Analog Layout, Analog Design and Physical Verification. Our dedicated and experienced team of engineers ensures delivery of high-quality results to accelerate clients' success. Trust in Radiant to illuminate your path to success. Why Radiant? 🌟 Competitive Salary & Benefits 📈 Career Growth Opportunities 🤝 Collaborative Work Environment 🎯 Cutting-Edge Projects We have Job Opportunity for Manager / Senior Role Physical Design Engineer Experience – 10 to 20+ Yr Location – Hyderabad Notice Period – Immediate to 30 Days Job Description IP/Block level PnR activities from Netlist to GDS-II Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure (STA), signoff checks like FEV, VCLP, EMIR and PV. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file Experience in signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff. Knowledge of high performance and low power implementation methods is preferred. Expertise in ICC2/Fusion Compiler/Innovus Worked on 5nm and below tech nodes experience preferred. Knowledge of tcl scripting skills.
Radiant Semiconductors is a global player in Semiconductor Industry Founded in 2018, offering tailored semiconductor solutions to meet clients' needs, Headquarters in Bengaluru, Hyderabad and USA. Our services are RTL Design, ASIC Verification, Physical Design, DFT, Analog Layout, Analog Design and Physical Verification. Our dedicated and experienced team of engineers ensures delivery of high-quality results to accelerate clients' success. Trust in Radiant to illuminate your path to success. Why Radiant? 🌟 Competitive Salary & Benefits 📈 Career Growth Opportunities 🤝 Collaborative Work Environment 🎯 Cutting-Edge Projects We have Job Opportunity for Senior Role Verification Engineer Experience – 10 to 20+ Yrs Location – Hyderabad Availability – Immediate to 15 Days Job Description Writing functional coverage models based upon the DV Plan Writing assertion or scoreboard-based checkers Analysing digital and functional coverage metrics Developing UVC’s and UVM tests as needed to close coverage gaps Experience in PCIe/ UCIe/Ethernet/DDR/ AMBA/ CPU
You have a job opportunity for the Manager / Senior Role Physical Design Engineer position in Hyderabad. Your primary responsibilities will include: - Performing IP/Block level PnR activities from Netlist to GDS-II - Demonstrating good knowledge of all PnR activities such as Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Executing all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handling signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Having knowledge of high performance and low power implementation methods (preferred) - Expertise in ICC2/Fusion Compiler/Innovus - Working on 5nm and below tech nodes experience (preferred) - Possessing tcl scripting skills About Radiant Semiconductor: Radiant Semiconductors, a global player in the Semiconductor Industry founded in 2018, offers tailored semiconductor solutions to meet clients" needs with headquarters in Bengaluru, Hyderabad, and the USA. The services provided by Radiant include RTL Design, ASIC Verification, Physical Design, DFT, Analog Layout, Analog Design, and Physical Verification. The dedicated and experienced team of engineers at Radiant ensures the delivery of high-quality results to accelerate clients" success. Trust in Radiant to illuminate your path to success. Why Radiant - Competitive Salary & Benefits - Career Growth Opportunities - Collaborative Work Environment - Cutting-Edge Projects This job opportunity requires 10 to 20+ years of experience and an immediate to 30 days notice period.,
Role Overview: As an Analog Layout Engineer at Radiant Semiconductors, you will be responsible for designing and implementing analog layouts for high-performance circuits such as amplifiers, ADCs, DACs, and voltage regulators using TSMC/Samsung 7nm and below nodes. Your role will involve ensuring design compliance by performing design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC). Key Responsibilities: - Design and implement analog layouts for high-performance circuits using TSMC/Samsung 7nm and below nodes - Perform design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC) Qualifications Required: - 3 to 8 years of experience in analog layout design at advanced nodes (TSMC/Samsung 7nm and below) - Proficiency in layout tools like Cadence Virtuoso, Synopsys IC Compiler, or similar - Understanding of layout-dependent effects (LDE) and its impact on performance - Knowledge of parasitic extraction, simulation, and optimization - Familiarity with design for manufacturability (DFM) techniques - Knowledge of Basic SKILL/PERL (Note: The company details were not provided in the JD.),
As a Physical Design Engineer with full chip implementation expertise, including PnR, STA, and signoff flows, your role will involve working on advanced technology nodes and taking ownership from netlist to GDS-II. Key Responsibilities: - Execute full-chip PnR activities from Netlist to GDS-II - Hands-on experience in Floor-planning, Placement, CTS, Routing, Timing Closure (STA) - Perform signoff checks: FEV, VCLP, EMIR, PV - Work on Physical Synthesis through Sign-off GDS2 file generation - Manage signoff convergence, block-level timing signoff, ECO generation, and power signoff - Knowledge of high-performance and low-power implementation methods - Expertise in ICC2 / Fusion Compiler / Innovus - Experience on 5nm and below technology nodes preferred - Good knowledge of Tcl scripting Skills Required: - Full-chip PnR, Floor-planning, CTS, Routing - STA, Timing Closure, Signoff (FEV / VCLP / EMIR / PV) - Physical Synthesis to GDS-II - ICC2 / Fusion Compiler / Innovus - Tcl scripting - 5nm and below node experience (preferred) - High-performance & low-power implementation methods If you are looking for a challenging role as a Physical Design Engineer with a focus on full chip implementation and advanced technology nodes, this opportunity could be the right fit for you.,