Physical Design Engineer

As a Physical Design Engineer with full chip implementation expertise, including PnR, STA, and signoff flows, your role will involve working on advanced technology nodes and taking ownership from netlist to GDS-II. Key Responsibilities: - Execute full-chip PnR activities from Netlist to GDS-II - Hands-on experience in Floor-planning, Placement, CTS, Routing, Timing Closure (STA) - Perform signoff checks: FEV, VCLP, EMIR, PV - Work on Physical Synthesis through Sign-off GDS2 file generation - Manage signoff convergence, block-level timing signoff, ECO generation, and power signoff - Knowledge of high-performance and low-power implementation methods - Expertise in ICC2 / Fusion Compiler / Innovus - Experience on 5nm and below technology nodes preferred - Good knowledge of Tcl scripting Skills Required: - Full-chip PnR, Floor-planning, CTS, Routing - STA, Timing Closure, Signoff (FEV / VCLP / EMIR / PV) - Physical Synthesis to GDS-II - ICC2 / Fusion Compiler / Innovus - Tcl scripting - 5nm and below node experience (preferred) - High-performance & low-power implementation methods If you are looking for a challenging role as a Physical Design Engineer with a focus on full chip implementation and advanced technology nodes, this opportunity could be the right fit for you.,