27 Tcl Scripting Jobs

As part of the ASIC modeling team, you will be responsible for developing, maintaining, and testing the NAND/SoC models using C/C++/SystemC. The SoC models aim to accurately capture the functionality of the controller chip that oversees the NAND storage. You should have 4 to 7 years of experience and possess expertise in DFT implementation and verification. Additionally, experience in MBIST implementation and verification, along with a strong grasp of DFT/MBIST fundamentals, is essential. You will be involved in tasks such as DRC Clean up, coverage improvement, and modifying MBIST algorithms. It would be beneficial to have knowledge in PERL/TCL Scripting/Python and using assertions for monitoring clock frequencies and test-related registers. Familiarity with yield analysis and improvement flow, understanding CLP constructs, and working in multi-voltage, multi-power design environments will be advantageous. Your expected roles will include architecting DFT based on the PETE, Design, and Customer specifications. A self-motivated, self-driven attitude with a thirst for learning is desirable for this position. The ideal candidate should hold a BE/Btech/Mtech/ME degree. Western Digital values diversity and believes that embracing various perspectives leads to the best outcomes. The company is dedicated to creating an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution. Western Digital is committed to providing equal opportunities to applicants with disabilities. If you require accommodations during the application process, please contact us at staffingsupport@wdc.com with details of your request, including the job title and requisition number.,

Qualcomm India Private Limited is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and driving digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 3+ years of Hardware Engineering experience, or a Master's degree with 2+ years of experience, or a PhD with 1+ year of experience. Key responsibilities include complete ownership of PNR implementation, including Floorplanning, Placement, CTS, post_route, etc., on the latest nodes. Signoff knowledge is mandatory, covering areas such as STA, Power analysis, FV, low power verification, PV, etc. The ideal candidate will possess hands-on experience with Floorplanning, PNR, and STA flows, as well as knowledge of Placement/Clock Tree Synthesis, optimization, and signoff domains like LEC/CLP/PDN. Qualifications for this role include a minimum of 5 years of Hardware Engineering experience or related work experience, along with 5 years of experience with PNR flow in the latest tech nodes (e.g., 4nm/5nm/7nm/10nm). A successful candidate should be a quick learner with strong analytical and problem-solving skills. Qualcomm is an equal opportunity employer committed to providing accessibility for individuals with disabilities during the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Please note that Qualcomm expects its employees to comply with all applicable policies and procedures, including security measures for protecting confidential information. Additionally, individuals seeking a job at Qualcomm should use the official Careers Site, as staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes. For further information about this role, please reach out to Qualcomm Careers.,

As part of a diverse team at Google, you will be working on developing custom silicon solutions for direct-to-consumer products. Your role will involve contributing to the innovation that drives products loved by millions globally, shaping the future of hardware experiences with a focus on performance, efficiency, and integration. You will specifically be involved in the development of a cutting-edge Application-specific integrated circuit (ASIC) aimed at accelerating machine learning computation in data centers. Working collaboratively with various teams such as architecture, verification, power and performance, and physical design, you will be responsible for specifying and delivering high-quality designs for next-generation data center accelerators. Your problem-solving skills will be put to the test as you tackle technical challenges using innovative micro-architecture and practical logic solutions, while evaluating design options with considerations for complexity, performance, power, and area. The Technical Infrastructure team at Google is responsible for the architecture that supports everything users see online. From maintaining data centers to building future Google platforms, this team plays a crucial role in enabling Google's product portfolio. As part of this team, you will be involved in defining and driving the implementation of physical design methodologies, taking ownership of design partitions or top-level, ensuring the closure of timing and power consumption aspects of the design, contributing to design methodology, libraries, and code reviews, as well as defining physical design-related rule sets for functional design engineers.,

Your team The PLM team consists of 9 people spread between Veghel and Pune, India. The members are multi-disciplinary, including both technical and functional specialists. The PLM team is part of the ICT Platform and Technology Solutions department. This department focusses on delivery of services which are used for the development and lifecycle management of multi-disciplinary Vanderlande products. Required Skills & Competencies: Good knowledge of Enovia PLM (2016x onwards) Proficient in Core Java and JavaScript, JSP, Customization of UI3 Component, triggers, TCL Scripting, MQL. Knowledge of TVC (Technia Value Component) will be an added advantage. Experience in developing Web Services using SOAP and RESTFUL Services. Knowledge of Exalead search and its configuration. Knowledge of integration with Solidworks. Knowledge of build tools such as Ant, Gradle, or Maven. Experience with version control systems like GIT or Sourcetree. Experience in working with Eclipse/IntelliJ IDE. Understanding of Agile methodology and Scrum practices. Strong communication and interpersonal skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Driving floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA Engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design Expect strong self-motivation and time management skills Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found . Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact .

Job Description: We are hiring an RTL Design Engineer with hands-on experience in FPGA-based RTL development. This role is focused on FPGA logic design and does not involve Silicon RTL or hardware testing . Key Responsibilities: RTL coding using Verilog, SystemVerilog, or VHDL Work on FPGA architecture and flow , including logic and digital design Scripting with Tcl and Python Perform synthesis and design stages using Vivado Collaborate with design teams to deliver high-quality IP blocks for FPGA

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and DFY, and Tapeout. You should have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep submicron processes, along with an understanding of process variation effects. Experience in variations analysis/modeling techniques and convergence mechanisms would be a plus. Proficiency in Synopsys ICC2 and PrimeTime physical design tools is essential for this role. Additionally, skill and experience in scripting using Tcl or Perl are highly desirable. Qualifications required for this position include a BE/BTech or ME/MTech degree with a specialization in the VLSI domain. The ideal candidate should have 5-10 years of relevant experience in the field.,

You will be part of Kinara, a Bay Area-based venture backed company, founded based on research conducted at Stanford University. Kinara's game-changing AI solutions aim to revolutionize what individuals and businesses can accomplish. Their Ara inference processors, combined with an innovative SDK, offer unparalleled deep learning performance at the edge. This enables the acceleration and optimization of real-time decision-making, emphasizing the importance of speed and power efficiency. By embedding high-performance AI into edge devices, Kinara contributes to creating a smarter, safer, and more enjoyable world. As the field of Edge AI is on the verge of a significant growth phase, Kinara is poised to play a pivotal role in this evolution. Your responsibilities will include the physical design of complex data path and control blocks, development of new techniques and flows for rapid hardware prototyping, creation of flows enabling detailed power estimation, collaboration with the design team to understand placement and recommend implementation options, as well as engagement with external teams to drive and deliver subsystems leading to chip tapeout. Preferred qualifications for this role include a BTech/MTech degree in EE/CS with at least 8 years of experience in Physical Design. You should possess extensive knowledge of Automated synthesis, Technology mapping, Place-and-Route, and Layout techniques, along with skills in Physical verification and quality checks such as LVS, DRC, IR drop, Clock tree synthesis, Power mesh design, and Signal integrity. Familiarity with the latest foundry nodes up to 7nm is desirable, as well as hands-on experience with various design aspects including Synthesis, Place-and-route, Full Chip STA, IO Planning, Floorplan, Power Mesh creation, Bump Planning, RDL Routing, and Low power design flows. Strong expertise in advanced digital design architectures and clocking structures is essential to manage timing and physical design constraints effectively. Furthermore, you should be able to collaborate with designers to analyze and explore physical implementation options for complex designs, possess basic knowledge of DFT techniques, and be familiar with industry-standard PnR, Synthesis, and TCL Scripting tools. Strong communication skills and the ability to work well in a team are also crucial. At Kinara, the work culture is centered around fostering innovation. The environment encourages professionals to tackle exciting challenges under the guidance of technology experts and mentors. The company values diverse perspectives and shared responsibilities, creating a collaborative and inclusive atmosphere where every individual's input is respected and appreciated. If you are passionate about making an impact and are eager to take on rewarding challenges, Kinara awaits your application eagerly. Join Kinara and be a part of a dynamic team that values innovation, collaboration, and personal growth. Your unique skills and experiences will contribute to shaping the future of AI solutions and advancing the field of Edge AI. Share your story with us, and let's work together to create a smarter, safer, and more enjoyable world.,

You are a FPGA design engineer with at least 5 years of experience, located in Vadodara, India. Your main responsibility is to implement control logic state machines and DSP algorithms in FPGA fabric for high throughput systems. You should possess excellent troubleshooting and debugging skills for both simulation and in-circuit scenarios. Your expertise should include: - Strong knowledge of digital design involving multiple clock domains - RTL design in Verilog and System-Verilog - Creating micro-architecture from high-level specifications - Functional simulation using ModelSIM or similar tools - FPGA design and synthesis, map and route flow, pin assignments, attribute assignments, resource fixing, and design partitioning - Targeting designs for Intel(Altera) or Xilinx FPGAs using Quartus Prime or Vivado - IP creation and parametrization using Vivado or Quartus - Debugging using ChipScope/SignalTap and lab bench oscilloscopes/protocol analyzers - Understanding of static timing analysis and timing closure using SDC - Collaborating with a cross-functional, global team of hardware designers, software engineers, verification and validation engineers - Leading teams to successful project completion within deadlines - Strong problem-solving skills It would be beneficial if you also have expertise in: - Knowledge of TCL scripting and Python - Transceivers and PHY - Power estimation and resource utilization estimation - Soft-processor cores like Microblaze or Nios-II - Understanding of Digital Signal Processing concepts - Proficiency in Matlab or Python for algorithm design - Familiarity with embedded systems/C/C++ About A&W Engineering Works: A&W Engineering Works is committed to developing and deploying innovative solutions to real-world problems. The company specializes in developing complete systems from front-end sensors to back-end applications, covering analog, digital signal processing, and algorithmic data and control paths. The team at A&W Engineering Works has a wide range of expertise in hardware, software, mechanical engineering, and systems development, aiming to solve complex problems efficiently with innovative development techniques and fast prototyping. To apply for this position, please send an email to [email protected] with your resume and cover letter attached, and remember to include the job title in the subject line.,

The culture at our organization is defined by the people who contribute to it. We foster a culture of passion for technology solutions that have a tangible impact on businesses. Additionally, we prioritize the pursuit of individual passions by our team members. Collaborating with us offers you the opportunity to gain a deep understanding of various industries and cutting-edge technologies. This knowledge enables us to develop forward-thinking and impactful solutions. Moreover, being a part of MarvyLogic can facilitate personal growth, leading you towards a more enriching and fulfilling life. To be considered for this role, you should possess the following qualifications: - A minimum of 10 years of experience in FPGA Design and Debug, preferably working with Xilinx Ultrascale+ and Virtex7 - Proficiency in utilizing tools such as Xilinx Vivado/Coregen/Synplify and developing/maintaining Timing/IO constraints (UCF) - Experience with managing multiple high-speed clock domains and integrating third-party IP onto Xilinx transceivers - Familiarity with working on FMC daughter-cards, High-Speed Cables/Connectors, etc. - Extensive debugging experience using Xilinx ILA, Protocol Analyzers, Oscilloscope, Logic Analyzers, etc. - Proficiency in PERL/TCL scripting and database management between FPGA and ASIC RTL - Knowledge of front-end RTL tools such as RTL Simulation, Synthesis, DFT, Timing - Ability to modify/adapt RTL designs for FPGA implementation and optimize designs to achieve FPGA area/performance goals - Collaboration with DV and Firmware/Software teams throughout the validation process, including post-silicon bring-up Your responsibilities in this role will include: - Effectively collaborating and communicating with multi-site teams - Reviewing FPGA netlist releases (block/chip) and overseeing ASIC product life cycle stages, including requirements, design, implementation, testing, and post-silicon validation If you meet the specified qualifications and are ready to take on these responsibilities, we welcome you to apply for this challenging and rewarding opportunity.,

You will be part of the SoC Clocking team, focusing on next-generation Networking and Edge SoC designs. Your responsibilities will include product pathfinding, end-to-end clocking architecture, clock distribution, and overseeing SoC clock implementation and Sign off. You should have experience in SoC Clock Architecture, clock distribution, and system-level clocking. Additionally, hands-on experience with spice, clock jitter simulations, and different jitter components is required. You will work on clocking methodologies and guidelines for IPs or SoCs and create scalable flows for clocking infrastructure to enhance performance and power in the design. Collaboration with Platform, package, IP, and SoC design teams is essential to drive best-in-class clocking solutions. A good understanding of Physical design and SoC timing analysis would be beneficial. Proficiency in Perl, TCL Scripting Skills is necessary. Qualifications - Bachelors (B.Tech) or Masters (M.Tech) in Electrical Engineering or related areas. - At least 18+ years of experience in SoC clock architecture, clock distribution, and clock implementation. - Hands-on experience with Synopsys, cadence APR/Clock implementation tools. - Good understanding of System-level clocking. - Proficient in scripting languages (Tcl, Perl, Python). - Ability to communicate effectively with multiple global cross-functional teams. This is an Experienced Hire job role with a requirement for on-site presence at Shift 1 (India). The primary location for this role is in India, Bangalore. Xeon and Networking Engineering (XNE) business group focuses on the development and integration of XEON and Networking SOC's and critical IP's to sustain Intel's Xeon and 5G networking roadmap. Please note that this role is a Position of Trust, requiring consent to and successful completion of an extended Background Investigation, which includes various checks. The work model for this role is subject to change.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with a minimum of 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience can also be considered. Additionally, candidates with a Bachelor's degree and 2+ years of experience, a Master's degree and 1+ year of experience, or a PhD with relevant experience are eligible. The ideal candidate should possess good hands-on experience in Floorplanning, PNR, and STA flows, as well as knowledge of Placement/Clock Tree Synthesis (CTS) and optimization. Familiarity with signoff domains such as LEC, CLP, and PDN is required, along with proficiency in Unix/Linux, Perl, TCL scripting. Key responsibilities include taking ownership of PNR implementation on the latest nodes, covering tasks like Floorplanning, Placement, CTS, and post-route activities. Signoff knowledge is crucial, encompassing areas like STA, Power analysis, FV, low power verification, and PV. A quick learner with strong analytical and problem-solving skills will excel in this role. Qualifications for this position include a minimum of 15 years of Hardware Engineering experience or related work experience, along with expertise in PNR flow for advanced tech nodes like 4nm, 5nm, 7nm, and beyond.,

Dear Candidate, We are hiring a Tcl Developer to build scripting solutions for automation, testing, and tool integrationespecially in EDA or network appliance domains. Key Responsibilities: Develop scripts and extensions using Tcl/Tk Automate test suites, hardware validation, or simulation environments Integrate with EDA tools, CI systems, or routers/switches Maintain internal tools and write documentation Collaborate with system engineers and QA teams Required Skills & Qualifications: Strong knowledge of Tcl/Tk scripting , GUI building, and tool automation Familiarity with Expect , Verilog simulators , or hardware flows Experience with UNIX/Linux environments Bonus: Background in networking or semiconductor industries Soft Skills: Strong troubleshooting and problem-solving skills. Ability to work independently and in a team. Excellent communication and documentation skills. Note: If interested, please share your updated resume and preferred time for a discussion. If shortlisted, our HR team will contact you. Kandi Srinivasa Reddy Delivery Manager Integra Technologies

T4S or T4ST, TCL Scripting and need Integration,• Design, configure, and implement T4ST integrations between Teamcenter and SAP for master data (Material, BOM, Document, etc.). T4x,TCL or JavaScript,SAP PLM integration and error handling.

Roles and Responsibilities Design, develop, test, and maintain scalable web applications using NodeJS, Perl, and Tcl. Collaborate with cross-functional teams to identify requirements and implement solutions that meet business needs. Ensure high-quality code by following best practices in coding standards, testing, and debugging. Participate in agile development methodologies such as Scrum to deliver projects on time. Troubleshoot issues related to backend development, frontend development, or full-stack development. Desired Candidate Profile 5-10 years of experience in IT industry with expertise in Fullstack Development (Backend & Frontend). Strong understanding of programming languages like NodeJS, Perl Programming, Tcl Scripting. Experience working with databases like PostgreSQL; knowledge of version control systems like GitHub. Educational qualification: B.Tech/B.E. degree from a recognized university.

Develop & support the Fidessa-based Cash Equities order management & execution platform enabling full trade lifecycle processing across global markets.Support highthrough put order Mgmt systems integral to equities trading Design & implement scalable Required Candidate profile Strong understanding of equities trading market microstructure & data normalization Tcl/Tk scripting,OA protocol; & reliable data stream architecture Unix Python; & Sybase DB Hands-on with CI/CD,Devop

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System. Able to handle multiple project execution that are time critical and complex Able to communicate effectively with all stakeholders across the organization Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution Focus on improving execution efficiency and improve on the optimizations in area, power and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate and bring fresh ideas Bachelor’s or master’s degree in engineering with 9-13+ Years of experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Responsibilities include Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus

Sr DFT Engineers and Managers - location remote any where in India Job Summary Our clients Arasan Chip Systems (www.arasan.com) based in US are seeking for their India Development Center Senior and Experienced DFT Engineer with 68 years of hands-on expertise in Design-for-Test methodologies and implementation for complex SoC designs. The candidate will be responsible for developing and integrating DFT architectures, driving ATPG and MBIST flows, and working closely with RTL design, physical design, and test teams to ensure high test coverage and silicon readiness. Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Generate and validate test patterns (stuck-at, transition, path delay). Collaborate with RTL, synthesis, and physical design teams to ensure DFT integration and timing closure. Participate in silicon bring-up and ATE support. Support internal reviews, audits, and DFT documentation. Skills Strong experience with industry-standard DFT tools (Mentor Tessent, Synopsys DFTMAX, Cadence Modus, etc.). Hands-on experience in scan insertion, ATPG, MBIST, boundary scan, and test compression techniques. Familiarity with ATE pattern generation and silicon debug flows. Solid understanding of RTL/gate-level simulation, synthesis, STA, and timing-aware DFT flows. Proficiency in scripting languages (TCL, Perl, Python) for automation. Excellent analytical and problem-solving skills. Qualifications B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field. 6–8 years of relevant experience in DFT for ASIC/SoC design. Preferred Exposure to low-power DFT methodologies (UPF/CPF flows). Prior experience with automotive or high-speed PHY IP integration is a plus. Knowledge of IEEE standards (1149.1, 1500, 1687).

An experienced PLM developer with in-depth knowledge of Teamcenter architecture, resource layer components such as DB and volume, Teamcenter Data Model, and database schema of Part, BOM, document management, and change management. Expertise in T4EA integration development to meet business and non-functional requirements. Proficiency in Teamcenter customization involving ITK, SOA, BMIDE, Rich Client plugin, and AWC. Programming experience in Teamcenter using C, C++, ITK, Java, XSL, XML, Angular JavaScript, TCL scripting, developing extensions, workflow handlers, and SOA services. Perform overall development, SVN management, JIRA management, production support, and maintenance activities. Create and maintain necessary documentation for the reports and integrations developed. Experience in developing business reports such as Bill of Material (BOM) comparison reports across systems, change management, drawing and document metadata, as well as integrating and transferring related dataset and its meta data to downstream, vendor and customer applications that are cloud and on prem hosted. Experience in authentication, authorization, and other security modules including Access Manager, ADA, and SSO integration. Experience in integrating Teamcenter with MCAD, ECAD, ERP, Polarion, and Rulestream. Proficiency in using JIRA & Confluence, Agile project methodology, and Sprint planning. Experience in Teamcenter deployment on cloud solutions like AWS, Azure, and Google Primary Skills Experience with Teamcenter integrations development. Experience with Active Workspace Client use. Experience in designing/architecting PLM/Teamcenter integration solutions including T4EA. Desired Experience Experience in using T4S / T4O for ERP Integration. Experience in using other OLAP, iPaaS like BOOMI, eQUBE -MI. Skills (competencies)

Experience : 3 to 10 Years Qualification : Bachelors or Masters (Electronics and Communication Engineering or equivalent) Job Description: As an Emulation Engineer, youll be an integral part of a dynamic team dedicated to creating cutting-edge ASIC solutions for High-Performance Computing (HPC) systems. Your role will involve defining the validation strategy leading to functional sign-off for these high-performance computing designs. Key functions and responsibilities: Proficient in various emulation technologies, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Familiarity with tools such as Palladium, Protium, Veloce, or Zebu. Good Knowledge of SystemC/C/C++ and UVM/SV verification languages Experience with SystemVerilog and C++ for modelling RTL components and transactors. Ability to develop C/C++/SystemC/SV tests in HDL-HVL (Hardware Description Language-Hardware Verification Language) Co-emulation platforms. Understanding of compilation and build flow. Skilled at building images from scratch, making necessary design modifications to adapt to emulation. Work closely with verification teams to define and implement comprehensive pre and post silicon test plans. Interface effectively with design, verification, validation, and software development teams to understand their needs from an emulation perspective. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip systems). Balancing performance and ease of debug. Proficient in post-silicon bring-up, debugging, and issue reproduction on emulators. Familiarity with Python and TCL scripting languages. Exposure to domains such as PCIe, CXL, DDR, Flash, Memory, USB, and CPU. Strong communication and collaboration skills to work effectively with cross-functional teams and domain experts. Successfully manage multiple design releases and provide support for debugging customer issues.

Relevant experience required (in years): 3+ years of IT experience. Your position Within Vanderlande, the primary tool for managing our product data is Enovia 3DEXPERIENCE. The PLM tool is highly integrated into the Vanderlande IT landscape, using our ESB. It acts as the product data backbone. In this position, you will be responsible for the quality of the PLM service for over 2000 active users, spread across around the world. We are seeking a motivated Enovia PLM resource with 3+ years of experience to join our team in Vanderlande, Pune. Your team The PLM team consists of 9 people spread between Veghel and Pune, India. The members are multi-disciplinary, including both technical and functional specialists. The PLM team is part of the ICT Platform and Technology Solutions department. This department focusses on delivery of services which are used for the development and lifecycle management of multi-disciplinary Vanderlande products. Required Skills & Competencies: Good knowledge of Enovia PLM (2016x onwards) Proficient in Core Java and JavaScript, JSP, Customization of UI3 Component, triggers, TCL Scripting, MQL. Knowledge of TVC (Technia Value Component) will be an added advantage. Experience in developing Web Services using SOAP and RESTFUL Services. Knowledge of Exalead search and its configuration. Knowledge of integration with Solidworks. Knowledge of build tools such as Ant, Gradle, or Maven. Experience with version control systems like GIT or Sourcetree. Experience in working with Eclipse/IntelliJ IDE. Understanding of Agile methodology and Scrum practices. Strong communication and interpersonal skills.

Relevant experience required (in years): 3+ years of IT experience. Your position Within Vanderlande, the primary tool for managing our product data is Enovia 3DEXPERIENCE. The PLM tool is highly integrated into the Vanderlande IT landscape, using our ESB. It acts as the product data backbone. In this position, you will be responsible for the quality of the PLM service for over 2000 active users, spread across around the world. We are seeking a motivated Enovia PLM resource with 3+ years of experience to join our team in Vanderlande, Pune. Your team The PLM team consists of 9 people spread between Veghel and Pune, India. The members are multi-disciplinary, including both technical and functional specialists. The PLM team is part of the ICT Platform and Technology Solutions department. This department focusses on delivery of services which are used for the development and lifecycle management of multi-disciplinary Vanderlande products. Required Skills & Competencies: Good knowledge of Enovia PLM (2016x onwards) Proficient in Core Java and JavaScript, JSP, Customization of UI3 Component, triggers, TCL Scripting, MQL. Knowledge of TVC (Technia Value Component) will be an added advantage. Experience in developing Web Services using SOAP and RESTFUL Services. Knowledge of Exalead search and its configuration. Knowledge of integration with Solidworks. Knowledge of build tools such as Ant, Gradle, or Maven. Experience with version control systems like GIT or Sourcetree. Experience in working with Eclipse/IntelliJ IDE. Understanding of Agile methodology and Scrum practices. Strong communication and interpersonal skills. About the Company: Vanderlande Website: Why should you join Vanderlande India Global Capability Center (GCC) We are certified as Great Place to Work by the prestigious Great Place to Work Institute. Flexible and Hybrid Workplace. Vanderlande Academy and training facilities to boost your skills. Mediclaim benefit including parental coverage. On-site company health centers with a gym, employee wellbeing sessions, in house doctor support. A variety in Vanderlande Network communities and initiatives. Opportunity to collaborate globally.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Requirements Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System. Able to handle multiple project execution that are time critical and complex Able to communicate effectively with all stakeholders across the organization Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution Focus on improving execution efficiency and improve on the optimizations in area, power and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate and bring fresh ideas Bachelors or masters degree in engineering with 9-13+ Years of experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Responsibilities include Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus 13+ Years experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). 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