Job Description: Details: Memory Design Engineer Job Requirement: We are looking to hire engineers with 2 to 10 years of experience in Memory design. Candidate needs to have comprehensive knowledge of circuit design with experience in developing CMOS memories such as SP SRAM, DP SRAM, Register File, and ROM. Should have understanding of process technologies and device behaviour and reliability issues Experience in o ptimizing performance, power, and area, reduce leakage of circuits, and drive characterization of individual memory instances and memory compilers. Understanding of SRAM PPA trade-offs is required Strong documentation skills and collaborative attitude are must haves Preferred Qualifications: Education - BE/ME/B.Tech/M.Tech Work location: Bangalore
Job Requirement: We are looking to hire engineers with 5 to 10 years of experience in Analog circuit design. Candidate needs to have comprehensive knowledge of Analog design with experience in some blocks like OpAmps, Comparators, Bandgap References, LC and ring oscillator, PLLs, CDR, LDO, Tx/Rx etc Should have understanding of process technologies and device behaviour and reliability issues, ESD and latchup Should have understanding of various aspects of signal integrity. Experience in Rx, Tx, T-coil ESD, CDR, equalization techniques like CTLE/DFE in PCIE or Ethernet is preferred. Strong documentation skills and collaborative attitude are must haves
Roles and Responsibility 5 years to 15 yrsdesign experience. Experience withowning chip level DFT and Post Silicon debug / analysis. Understanding of DFTarchitectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISRetc.), scan chain insertion and verification. Must have experiencegenerating scan patterns and coverage statistics for various fault models likestuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, patterngeneration for Memories(E-fuse etc.). Experience debugging tester failures ofscan patterns, diagnosis and pattern re-generation. Understandinggeneration of functional patterns for ATE Knowledge of atleast any one of an industry standard DFT tools (Cadence Modus, SynopsysTetramax, Mentor Tessent Tools, etc) Design experience inMBIST / LBIST is an added advantage. Good understandingof constraints development for Physical Design Implementation / Static TimingAnalysis. Responsibilities: Must have experience generating scan patterns andcoverage statistics for various fault models like stuck at(Nominal and VBOX),IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E- fuseetc.). Experience debugging tester failures of scan patterns, diagnosis andpattern re-generation. Understanding generation of functional patterns forATE Knowledge of at least any one of an industrystandard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools,etc) Design experience in MBIST / LBIST is an addedadvantage. Good understanding of constraints development forPhysical Design Implementation / Static Timing Analysis. Desired Skills: Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits andit s design cycles is an added advantage. Effective communication skills to interact with allstakeholders. Team and People Skills: The candidate should havegood people skills to work closely with the systems, analog, layout and testteam Must be highly focused and remain committed toobtaining closure on project goals Role: DFT Engineer Department: Design For Test & Debug Employment Type: Full Time, Permanent
Job Title: Linux Device Driver Engineer Location: Hyderabad, Telangana, India Job Summary: We are seeking a highly skilled and motivated Linux Device Driver Engineer to join our dynamic engineering team. You will be responsible for the design, development, testing, and debugging of device drivers for embedded Linux systems. Your work will be crucial in enabling seamless interaction between our hardware and software platforms. Responsibilities: Design and develop high-quality Linux device drivers for various hardware peripherals (e.g., sensors, communication interfaces like UART, SPI, I2C, network interfaces, storage devices). Work closely with hardware engineers to understand hardware specifications and functionalities. Implement kernel-level modules and ensure their stability, performance, and security. Develop and execute unit and integration tests to validate driver functionality. Debug and resolve issues related to device drivers in development and production environments. Optimize drivers for performance and resource utilization. Contribute to the development and maintenance of the build and integration processes. Stay up-to-date with the latest Linux kernel developments and relevant hardware technologies. Document design specifications, implementation details, and testing procedures. Collaborate effectively with other software engineers, hardware engineers, and QA teams. Qualifications: Mandatory hands on experience in developing Linux device drivers for basic peripherals like I2C, UART, SPI etc. Deep understanding of Linux internals like memory mapping, interrupt handling (top half, bottom half), Device tree concepts. Strong proficiency in Advanced C programming and a deep understanding of the Linux kernel architecture. Good knowledge of driver models such as the Linux Device Model, platform drivers, and bus-specific drivers (e.g., PCI, USB, I2C, SPI). Good to have experience in RTOS firmware programming. Familiarity with debugging tools such as GDB, kernel debugging techniques (e.g., printk, kernel crash dumps). Experience with build systems (e.g., Make, CMake, Yocto Project). Understanding of hardware interfaces and protocols. Excellent problem-solving and analytical skills. Strong communication and collaboration skills. Preferred Qualifications: Experience with real-time operating systems (RTOS) concepts. Contributions to open-source Linux kernel projects. Experience with specific hardware architectures (e.g., ARM, x86). Knowledge of scripting languages such as Python or Bash. Experience with virtualization technologies.
Advanced programming skills in C/C++ for operating system kernel & systems development Solid understanding and experience with the Windows Network or Storage Driver architecture, WDF & WDM. Good understanding of PCIe, I2C , UFS, NVMe protocols. Good working knowledge of Storport and NDIS miniport driver. Deep Knowledge of Computer Architecture and Windows Kernel Internals. Good understanding of operating systems concepts, data structures, x86-64 architecture. Proficient use of git Python, Shell Scripting, BIOS knowledge an added advantage
Mandatory Skills : 5-15 years of experience in the x86 BIOS/UEFI FSP/coreboot development Experience with x86 CPU/APU architectures and associated compilation tools Expert in C language Experience with platform bring-up Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff Working experience of industry standard protocols like PCIe, SPI, eSPI, ACPI, SMM Experience on working with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. Experience on working with Intel FSP package source code and understanding of coreboot & FSP boot flow Understanding of coreboot & FSP build tools and build processes Experience of working with different coreboot payloads like edk2, SeaBios, Tianocore etc Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required Good understanding of UEFI framework concepts to port UEFI code to FSP Additional Skillset : Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. Good understanding of x86-64 architecture from BIOS developers perspective. Good understanding of UEFI BIOS Boot flow. Basic understanding of Linux Kernel like software development concepts (Kconfig). We are seeking a talented and motivated Software Engineer to work on Vulkan/OpenGL/OpenCL libraries. As a key member of the graphics team, you will work on challenging and groundbreaking projects in the open-source domain and you will have the opportunity to collaborate with leading experts and contribute to the development of cutting-edge graphics technology. Responsibilities Develop high-performance, visually stunning graphics applications using OpenGL/Vulkan/OpenCL APIs. Troubleshoot and resolve complex graphics-related issues. Development of C++ based automotive applications. Conceptualization, prototyping, design, development & unit testing of application SW based on product requirement. Collaborate with cross-functional teams to implement innovative graphics solutions. Working with the extended team (developers & verification team) to enhance the application & functionality. Participate in debugging and troubleshooting to identify and address software (build, algorithm/ functionality/ dependency) issues. Required skills The ideal candidate possesses a strong foundation in C/C++, a deep understanding of OS concepts. Experience in integrating OpenGL/Vulkan/OpenCL to Graphics Processing Unit. Expertise in at least one graphics API (OpenGLES, Vulkan, or OpenCL) OR extensive experience for graphics development. GPU optimization experience. Add on: Past experience with Mesa 3D Graphics library.
Linux developers with hands-on experience developing Linux device drivers of 3 to 8 years. Working knowledge of any of the peripheral Linux drivers areas such as: USB, PCIe, HSIC, etc., DWC, USB Gadget drivers, Android USB drivers, USB host controller drivers. DMA client/controller driver development experience Experience in PCIe debug using Lecroy PCIe analyzer. Very good C programming and Linux skills. Good understanding of Linux OS concepts and Linux Kernel internals. Good system debugging skills and root cause analysis. Candidates should be familiar in understanding the peripheral hardware, Device Data sheets, Schematics, Specification and Reference manual. Some experience with Qualcomm chipset code, drivers, tools usage and system design. Preferably good understanding about ARM32/64 chipset architecture. Domain:- Boot-loader, Linux BSP, Device driver for PCIe, USB, etc JOB Description for Windows Drivers: Advanced programming skills in C/C++ for operating system kernel & systems development Solid understanding and experience with the Windows Network or Storage Driver architecture, WDF & WDM. Good understanding of PCIe, I2C , UFS, NVMe protocols. Good working knowledge of Storport and NDIS miniport driver. Deep Knowledge of Computer Architecture and Windows Kernel Internals. Good understanding of operating systems concepts, data structures, x86-64 architecture. Proficient use of git Python, Shell Scripting, BIOS knowledge an added advantage
Job description: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IPs on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 10-12 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory(eFlash/SRAM/eNVM design)) designs Experience in analog circuits Charge pumps, regulators, low voltage analog circuits, sense amplifier Good understanding and analysis of READ/PROGRAM/ERASE simulations and analysis General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. Role & responsibilities Preferred candidate profile
Required Skills & Experience 3 to 5 years of experience in IP/Subsystem/SoC design verification. Strong knowledge in SystemVerilog, UVM , and functional coverage. Understanding of digital design concepts (FSMs, pipelines, FIFOs, memory, clock/reset domains). Experience with protocols like AMBA (AXI/AHB/APB) or similar. Familiarity with assertion-based verification (SVA) . Hands-on with EDA tools (Cadence Xcelium, Synopsys VCS, Mentor Questa, or equivalent). Proficiency in debug tools (Verdi, SimVision, DVE). Strong problem-solving and debugging skills. Scripting skills in Python/Perl/TCL/Makefile for automation. Good to Have (Optional) Exposure to DFT/DFX verification, UPF/power-aware flows, or GLS . Experience with high-speed interfaces (PCIe, USB, DDR, UCIe, etc.) . Familiarity with C/C++/embedded software-driven verification . Role & responsibilities Location: Bangalore Looking for immediate joiners.
Required Skills & Experience 7 to 15 years of experience in IP/Subsystem/SoC design verification. Strong knowledge in SystemVerilog, UVM , and functional coverage. Understanding of digital design concepts (FSMs, pipelines, FIFOs, memory, clock/reset domains). Experience with protocols like AMBA (AXI/AHB/APB) or similar. Familiarity with assertion-based verification (SVA) . Hands-on with EDA tools (Cadence Xcelium, Synopsys VCS, Mentor Questa, or equivalent). Proficiency in debug tools (Verdi, SimVision, DVE). Strong problem-solving and debugging skills. Scripting skills in Python/Perl/TCL/Makefile for automation. Good to Have (Optional) Exposure to DFT/DFX verification, UPF/power-aware flows, or GLS . Experience with high-speed interfaces (PCIe, USB, DDR, UCIe, etc.) . Familiarity with C/C++/embedded software-driven verification . Role & responsibilities Location: Bangalore Looking for immediate joiners.
Role & responsibilities Design, develop, and maintain web applications using Java, Spring Boot, and React/Angular . Build and consume RESTful APIs and microservices. Work closely with cross-functional teams to define, design, and deliver features. Write clean, maintainable, and efficient code following best practices. Ensure performance, scalability, and security of applications. Deploy and monitor applications on Azure Cloud . Participate in code reviews , unit testing, and documentation.
Net framework + React - C#, ASP.Net, MVC, Microsoft SQL Server, RESTful APIs, Microsoft Azure, Frontend tech - React, HTML, CSS, Azure DevOps, GitHub Actions. Candidates should have worked in React for a minimum of 3 years.
Roles and Responsibilities: Perform RTL-to-GDSII implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. Work on P&R flows using tools such as Cadence Innovus / Synopsys ICC2 . Handle timing analysis and sign-off using PrimeTime / Tempus . Perform power planning, IR-drop, and EM analysis to meet reliability targets. Execute DFM closure DRC/LVS/ANT checks using Calibre . Implement ECOs for timing, functionality, and metal fixes. Work closely with front-end, verification, and DFT teams to ensure full-chip integration and timing convergence. Optimize Power, Performance, and Area (PPA) for block- and top-level designs. Contribute to flow automation and scripting using TCL/Perl/Python. Support low-power design methodologies (UPF/CPF) and clock/power gating techniques. Participate in design reviews, timing sign-off , and final GDS tape-out. Responsible for block-level and full-chip implementation on advanced process nodes (7nm/5nm/3nm). Preferred Tools: Physical Design: Cadence Innovus / Synopsys ICC2 STA: PrimeTime / Tempus Sign-off: Calibre, Voltus, RedHawk Extraction: StarRC / Quantus Scripting: TCL, Perl, Python
Job Description: We are looking for a Lead STA (Static Timing Analysis) Engineer to join our semiconductor design team. The ideal candidate will have extensive experience in ASIC/SoC timing analysis, closure, and signoff , along with deep knowledge of industry-standard tools like PrimeTime or Tempus . You will be responsible for driving timing closure , ensuring robust design constraints, and collaborating with Physical Design, Synthesis, and Signoff teams to deliver high-performance silicon. Roles and Responsibilities: Perform Static Timing Analysis (STA) across multiple corners and modes (MMMC). Debug and resolve setup, hold, recovery, and removal violations. Own and maintain timing constraint files (SDC) throughout the flow. Drive timing closure from pre-CTS to post-route and final signoff stages. Work with Physical Design and RTL teams to fix timing through ECO implementation . Conduct timing correlation and path-based analysis between synthesis and post-route stages. Collaborate with cross-functional teams Clock, Power, DFT, RTL, and Signoff engineers. Support signoff timing verification and ensure design meets PPA (Performance, Power, Area) goals. Develop TCL/Perl/Python scripts to automate timing report generation and analysis. Provide detailed timing closure reports and updates to project managers and stakeholders.
Job Description: We are looking for highly motivated interns and early graduates passionate about AI, Machine Learning, and Large Language Models (LLMs) to join our Data Science team. You will work on real-world problems involving GenAI, NLP, model fine-tuning, and data-driven insights , collaborating with experienced ML engineers and data scientists. Responsibilities: Assist in building and fine-tuning LLMs, NLP, and GenAI-based models . Work on data preprocessing, feature engineering, and model evaluation . Collaborate with cross-functional teams to integrate models into applications. Analyze datasets using Python, Pandas, NumPy, and visualization tools . Research and experiment with prompt engineering and open-source LLMs (Llama, GPT, Mistral, etc.). Document and present findings to the core AI team.
PD CAD Job Description Supporting Place and Route workflows for designs at 6nm, 4nm, and 3nm technology nodes. Qualifying tool versions and deploying new features into the workflow. Solid understanding of low power flows. Updating current workflows to incorporate new capabilities as needed. Proficient with Synopsys Fusion Compiler or ICC2/Cadence Innovus PnR tool.. Strong grasp of scripting languages like PERL and TCL, along with robust debugging skills. Experienced in synthesis, Place and Route workflows, as well as STA tools. Skilled in using physical verification tools. Basic Job Deliverable PnR flow qualification, PnR flow support, running multiple PnR blocks to benchmark, PPA push, design correlation with STA, EMIR, PDV signoff flows Qualification BTech / MTech / BE / ME Experience Level 6 to 10 years
ob Title: Design Verification Engineer (5-7 YOE) Positions: 3 Nos Key Responsibilities Develop and implement test plans, test benches, and verification environments for MIPI, NoC, and subsystem-level designs. Work on UVM-based constrained random verification and functional coverage closure. Define verification strategy and drive verification sign-off for assigned subsystems. Debug design and testbench issues at block, subsystem, and SoC levels. Collaborate with design, architecture, and validation teams to ensure coverage completeness and timely bug closure. Contribute to automation frameworks and continuous integration flows for regression. Drive functional/performance verification of MIPI protocols (e.g., CSI, DSI, UniPro, UFS). Validate NoC interconnect fabric including throughput, latency, QoS, and corner-case scenarios. Engage in subsystem-level verification, integrating multiple IPs and validating end-to-end use cases.
Role & responsibilities Java Fullstack Developer Java Fullstack Developer Min 6 to 12 years of experience in Advance JAVA, Spring Boot, Microservices and React JS development JAVA-8 or 11 Level3 React JS experiance Spring Boot with Microservices Any SQL Kafka, Docker, Kubernetes, Docker, Splunk SpringFrame work, JPA/Hibernate Rest API with Spring boot GIT, Jenkins, Maven/or build tool Mandatory Skills: Fullstack Java Enterprise .
Role Purpose The purpose of the role is to support process delivery by ensuring daily performance of the Production Specialists, resolve technical escalations and develop technical capability within the Production Specialists. Do Key Responsibilities • Develop responsive and dynamic UIs using React.js, TypeScript, and modern frontend frameworks. • Integrate Generative AI APIs (e.g., OpenAI, Azure OpenAI, Hugging Face) into user-facing applications. • Build and deploy chatbots, assistants, NLP workflows using frameworks like LangChain, Streamlit, or Chainlit. • Collaborate with backend engineers to connect GenAI outputs to visualization tools or custom dashboards. • Optimize performance, scalability, and security of AI-driven applications. • Participate in Agile development cycles, code reviews, and design discussions. • Stay current with GenAI research and contribute to experimentation and model selection. Required qualifications • 6+ years of experience in frontend development with React.js, JavaScript/TypeScript. • Hands-on experience with Generative AI APIs, prompt engineering, and LLM integration. • Familiarity with backend technologies such as Node.js, Python, or Spring Boot. • Understanding of RESTful APIs, OAuth, and cloud services (Azure, AWS, or GCP). • Experience with version control, CI/CD pipelines, and containerization (Docker/Kubernetes). • Strong problem-solving and communication skills. Good to Have • Experience with LLM fine-tuning, RAG systems, or custom model deployment. • Knowledge of vector databases, and data pipelines. • Awareness of ethical AI practices, including bias mitigation and responsible use. Deliver NoPerformance ParameterMeasure1ProcessNo. of cases resolved per day, compliance to process and quality standards, meeting process level SLAs, Pulse score, Customer feedback, NSAT/ ESAT2Team ManagementProductivity, efficiency, absenteeism3Capability developmentTriages completed, Technical Test performance Mandatory Skills: Fullstack MERN .
Experience Required 8-15 Years in CPU/SoC design verification Key Responsibilities Verification Strategy & Planning Develop comprehensive verification plans and strategies for RISC-V CPU cores (in-order and out-of-order pipelines) Define coverage metrics and create detailed test plans for microarchitectural features Drive verification closure through coverage analysis and corner case identification Test Development & Execution Design and implement constrained random test benches using SystemVerilog/UVM Develop directed tests for critical CPU features: pipeline stages, branch prediction, cache coherency, memory management unit (MMU), and interrupt handling Create assembly-level tests targeting RISC-V ISA compliance (RV32/RV64, extensions: M, A, F, D, C, V) Build and maintain regression test suites with automated checking mechanisms Debug & Root Cause Analysis Debug complex functional and performance issues in CPU RTL designs Perform waveform analysis and work closely with design teams to identify and resolve bugs Track and manage bug reports through resolution and silicon correlation Coverage & Quality Metrics Implement functional coverage models for CPU microarchitecture Achieve code coverage targets (line, toggle, FSM, assertion coverage) Drive coverage closure activities and identify verification gaps Methodology & Tools Build and enhance verification infrastructure using industry-standard tools Develop reusable verification components and methodology improvements Mentor junior engineers on verification best practices Required Qualifications Technical Skills Strong expertise in CPU microarchitecture (pipelines, caches, branch prediction, speculation, out-of-order execution) Deep knowledge of RISC-V ISA specifications and extensions (RV32/RV64, M/A/F/D/C/V) Advanced proficiency in SystemVerilog, UVM methodology, and assertion-based verification (SVA) Experience with formal verification tools and techniques Hands-on with industry-standard EDA tools (VCS, Verdi, Questa, IUS/Xcelium) Solid understanding of cache coherency protocols (MESI/MOESI) and interconnect fabrics Knowledge of memory subsystems, MMU/TLB, and virtual memory concepts
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