Posted:8 hours ago|
Platform:
Work from Office
Full Time
Roles and Responsibility 5 years to 15 yrsdesign experience. Experience withowning chip level DFT and Post Silicon debug / analysis. Understanding of DFTarchitectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISRetc.), scan chain insertion and verification. Must have experiencegenerating scan patterns and coverage statistics for various fault models likestuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, patterngeneration for Memories(E-fuse etc.). Experience debugging tester failures ofscan patterns, diagnosis and pattern re-generation. Understandinggeneration of functional patterns for ATE Knowledge of atleast any one of an industry standard DFT tools (Cadence Modus, SynopsysTetramax, Mentor Tessent Tools, etc) Design experience inMBIST / LBIST is an added advantage. Good understandingof constraints development for Physical Design Implementation / Static TimingAnalysis. Responsibilities: Must have experience generating scan patterns andcoverage statistics for various fault models like stuck at(Nominal and VBOX),IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E- fuseetc.). Experience debugging tester failures of scan patterns, diagnosis andpattern re-generation. Understanding generation of functional patterns forATE Knowledge of at least any one of an industrystandard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools,etc) Design experience in MBIST / LBIST is an addedadvantage. Good understanding of constraints development forPhysical Design Implementation / Static Timing Analysis. Desired Skills: Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits andit s design cycles is an added advantage. Effective communication skills to interact with allstakeholders. Team and People Skills: The candidate should havegood people skills to work closely with the systems, analog, layout and testteam Must be highly focused and remain committed toobtaining closure on project goals Role: DFT Engineer Department: Design For Test & Debug Employment Type: Full Time, Permanent
Aritrak Technologies
Upload Resume
Drag or click to upload
Your data is secure with us, protected by advanced encryption.
Bengaluru
0.5 - 0.6 Lacs P.A.
Bengaluru
7.2 - 16.2 Lacs P.A.
Bengaluru
3.0 - 8.0 Lacs P.A.
Haldia
5.0 - 8.0 Lacs P.A.
3.0 - 7.0 Lacs P.A.
Bengaluru
0.5 - 0.6 Lacs P.A.
1.5 - 3.0 Lacs P.A.
Experience: Not specified
2.0 - 3.5 Lacs P.A.
2.25 - 3.0 Lacs P.A.
Experience: Not specified
0.5 - 2.0 Lacs P.A.