Dft Design Engineer

We are looking for an experienced DFT Lead / Architect with a proven track record of DFT architecture, implementation and verification at SoC level. The ideal candidate will have the ability to build and lead a high-performing DFT team while delivering world-class DFT solutions for complex chips.

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Key Responsibilities

DFT Architecture & Strategy

Define and develop DFT architecture concepts at SoC level.

Work with technical leads to define test modes to optimize test time.

Define MBIST algorithms, grouping and top-level MBIST strategies for optimal test coverage.

DFT Implementation

Define scan length and insert SCAN chains.

Generate EDT compactors and integrate into RTL clusters/macros.

Generate TAP controllers, test mode entry and data registers for macros.

Generate and integrate BIST controllers into RTL design.

Insert and generate boundary SCAN chains on IO pads.

Verification & Test Pattern Generation

Verify DFT logic and components at top level in RTL mode.

Generate high-quality test & debug patterns including stuck-at & transition faults.

Assess & optimize fault coverage (98% without fault dictionary exclusion).

Perform static timing analysis of DFT modes including scan shift & capture.

Restimulate patterns in gate-level simulations across multiple corners; debug setup/hold violations.

Automation & Test Enablement

Establish pattern generation flows (MBIST, BSCAN, SCAN, functional patterns) for test team autonomy.

Support test pattern debugging on testers post-silicon.

Team Leadership

Build, mentor and manage a team of DFT engineers.

Define team goals, review technical deliverables, and ensure on-time project execution.

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Required Skills

Minimum 10+ years of experience in DFT design, implementation and verification for complex SoCs.

Proven experience in building and leading DFT teams.

Strong knowledge of Chip Design, Verilog, SystemVerilog.

Hands-on expertise with ATPG tools, Scan insertion tools, MBIST, Boundary Scan, BIST.

Proficiency in Gate-level simulations and Static Timing Analysis for DFT modes.

Experience with UVM methodology for verification.

Strong scripting skills (Perl, Tcl) for automation.

Excellent communication and cross-functional collaboration skills.

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Preferred / Nice to Have

Experience in high-volume production test support and silicon bring-up.

Familiarity with fault diagnosis & yield improvement strategies.