73 Bist Jobs

Understand the design specification, Power On Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verificationChip reset sequence and initialization, and/or Power management. Knowledge of verification methodology, Knowledge of HDLs (VHDL,Verilog) Good programming skills in C++/C/OOPs, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge High Speed Serdes Phy, PCIe, DDR, Ethernet protocol Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

About The Role About The Role Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing, integrating and verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functional teams interaction for issue resolution. Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability. Hiring candidate with these specific personal characteristic and qualifications. Mentoring junior engineers and drive innovation/automation. Excellent in problem solving and analytical skills. Excellent communication, team work and networking skills. Primary Skills Should Have Good understanding of Design and DFT Architecture. Should have been part of atlest 3 Tapeout SoC. Well Versed with ATPG Tools & MBIST Tools. Secondary Skills Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders). Familiarity with Desired Flexibility and adaptability with respect to project management.

Job Description: We are looking for DFT Engineers with 3+ years of experience in Scan, MBIST, and ATPG. The role involves developing and implementing advanced DFT methodologies to ensure testability and high-quality silicon. Key Responsibilities: Hands-on experience with Scan insertion and Scan DRC/Coverage debug. Strong background in ATPG pattern generation and fault coverage analysis. Expertise in Gate-level simulations (Zero delay / Timing delay simulations). Worked on JTAG protocols. Experience in MBIST insertion, verification, and debug. Proficiency in Perl/Tcl scripting for automation of flows. Familiarity with timing verification, formal verification, and PD flow (a plus). Ability to debug and optimize DFT implementation for quality silicon.

General Summary: Minimum 4 to 6 years of work experience in ASIC RTL Design. Strong expertise in MBIST insertion, Scan insertion, and ATPG. Proficiency with SMS MBIST insertion tool is mandatory. Must have hands-on experience with handling sub systems with multiple memory types and grouping. Additional experience in memory redundancy, BIRA analysis, and repair solutions is highly desirable. Solid understanding of multi-memory bus interfaces and functional safety BIST requirements is a strong advantage. Exposure to Automotive System Designs, Memory Controller Designs, and Microprocessors is a plus. Experience in low power design and synthesis/timing concepts for ASICs is preferred Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities/job duties Memory Frontend Model development/verification/delivery/debug/Automation Memory Front End team introduction: At Qualcomm memory team, we specialize in front-end modeling for a wide range of memory IPs. This includes various architectures such as single-port memories, pseudo dual-port designs, register files, CPU memories, and complex custom memories developed from the ground up. Each IP development undergoes comprehensive verificationcovering functional, formal, BIRA, and DFT domainsand is rigorously validated through an extensive QA suite to ensure alignment with the actual memory circuit implementation Qualifications Masters in Electronics and communication Engineering or Electrical Engineering or related field with 0-2 years experience. In this position candidate will be part of memory FrontEnd modelling team where he/she will be responsible for below: Design and implement behavioral models in Verilog/System Verilog for compiler-generated and custom memory components. Maintain and enhance memory compilers to ensure accurate generation of behavioral Verilog models. Develop and support LVLIB and MASIS models for memory BIST (Built-In Self-Test) applications. Create FPGA-compatible models tailored for emulation platforms. Build DFT (Design-for-Test) and Fast Scan models to support comprehensive test coverage. Execute signoff simulations for both functional and formal verification across all compiler and custom memory models. Run comprehensive QA suites to validate that all memory models accurately reflect the intended circuit implementations. Develop and maintain signoff verification tools and QA automation frameworks for memory model validation. Conduct post-release QA checks to ensure model quality and reliability. Manage customer releases , ensuring readiness and documentation. Provide support to SoC teams , assisting with debugging and resolving memory interface issues related to the models. In this position, candidates should have below understating and hands on experience: Strong understanding of memory architecture and functionality. Solid grasp of CMOS low-power circuit design principles. Proficient in simulation tools such as Vsim, VCS, Finesim, and CustomSim. Deep expertise in Verilog and System Verilog coding practices. Familiarity with BIST modeling frameworks like LVLIB and MASIS. Good working knowledge of CLP and Static Timing Analysis (STA). Experience with Unix, Shell scripting, Perl, and Python is a plus. Excellent communication and collaboration skills.

The role at Ceremorphic AI hardware involves owning and driving the physical implementation of next-generation SOCs. The responsibilities include understanding requirements, defining physical implementation methodologies, collaborating with various teams, implementing and verifying designs, interacting with foundry, and supervising resource allocation and scheduling. The ideal candidate should have hands-on expertise in floorplanning, power planning, logic and clock tree synthesis, placement, timing closure, routing, extraction, physical verification (DRC & LVS), crosstalk analysis, and EM/IR. Additionally, full chip/top-level expertise in multiple chip tape-outs, understanding of SCAN, BIST, and ATPG, strong background in TCL/Perl programming, and expertise in double patterning process nodes are required. Preferably, expertise in Cadence RTL-to-GDSII flow is also desired.,

Understand the design specification , Memory and Memory BIST engine connections Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debu

Lead a team of 5-10 resources Understand the design specification , PowerOn Specification Understand boot firmware and reset flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization. ( for SoA) Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

You should have a minimum of 4 years of experience in the field. You must be proficient in using Synthesis and netlist validation tools, particularly LEC and Spyglass checks, as well as scan insertion and DRC debug. It is essential to be well-versed in both Synopsys and Mentor Graphics DFT flows. Your expertise should also include experience in Scan Compression for Hierarchical and Modular EDT, ATPG, and Coverage debug, along with the ability to manage multiple clock domains and familiarity with the OCC flow. You should have practical experience in BIST and BISR insertion and Validation with SMS and MBIST Architect. Hands-on experience with JTAG, IJTAG, and SSN is required. You should be familiar with P1500 and have experience in managing wrapper cells and test integration. Knowledge of INTEST and EXTEST modes, as well as working knowledge on Cell Aware ATPG, is important for this role. Additionally, strong communication and Automation skills are a must for this position.,

Understand the design specification , PowerOn Specificatio Understand boot firmware and reset flow Develop skills in IBM BIST verification tools and apply them successfull Develop the verification environment and test benc Debug fails using waveform, trace tools and debug RTL cod Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise 4+ years of experience in Design Verification - demonstrated execution experience of verification of logic block Strong in SoC verification Chip reset sequence and initialization. ( for SoA Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL Good programming skills in C/C++, Python/Per Exposure in developing testbench environment, write complex test scenario, debugging and triaging fail Hardware debug skills backed by relevant experience on project Exposure in developing testbench environment, write complex test scenario Good communication skills and be able to work effectively in a global team environmen Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plu Scripting Expertise backed up relevant experience in the sam Writing Verification test plan Functional and code coverage analysis and debug

Understand the design specification , Memory and Memory BIST engine connection Develop skills in IBM BIST verification tools and apply them successfull Develop the verification environment and test benc Debug fails using waveform, trace tools and debug RTL cod Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 4+ years of experience in Design Verification - demonstrated execution experience of verification of logic block Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIS Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL Good programming skills in C/C++, Python/Per Exposure in developing testbench environment, write complex test scenario, debugging and triaging fail Hardware debug skills backed by relevant experience on project Exposure in developing testbench environment, write complex test scenario Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the sam Writing Verification test plan Functional and code coverage analysis and debug

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Cadence tools,scan insertion,JTAG,ATPG,DRC,coverage analysis,simulation debug,timing,SDF,LBIST,Mixed Signal Radar IC,proactive,collaborative,detail-oriented,independent judgment,debug,root cause analysis,Verilog*

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills JTAG,ATPG DRC,LBIST,RTL coding,VHDL,DFT

What Youll Be Doing: Working closely with a world-class R&D team, youll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM), Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development, Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment, Driving the deployment and smooth execution of SLM solutions into customersprojects, Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations, The Impact You Will Have: Enhancing SynopsysSilicon Lifecycle Management (SLM) IP portfolio and end-to-end solution, Driving the adoption of SynopsysSLM solutions at premier customer base worlwide, Influencing the development of next-generation SLM IPs and solutions, What Youll Need: BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field, 4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both, Good knowledge of AXI, APB Background in verification, with at least sub-system level verification Debugging abilities to identify issues in functional verification, Knowledge of DMA, ideally should have verified a sub-system with DMA Knowledge of High-speed IO sub-systems like PCIe and USB A thorough understanding of memory mapping concepts is essential, End to end knowledge of how transactions/data flow between the HSIO interface to/from memory Knowledge and experience with Memory BIST/DFT/ATE/SLT/any other test solutions Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions

We are looking for a skilled DFT Engineer with 3 to 7 years of experience to join our team in the IT Services & Consulting industry. The ideal candidate will have a strong background in designing and implementing fault detection and testing strategies. Roles and Responsibility Design and develop test plans, test cases, and test scripts for complex systems. Collaborate with cross-functional teams to identify and prioritize testing requirements. Develop and maintain automated testing frameworks and tools. Analyze test results, identify defects, and work with development teams to resolve issues. Participate in agile development methodologies and contribute to process improvements. Stay up-to-date with industry trends and emerging technologies in DFT engineering. Job Requirements Strong understanding of digital logic design principles and microelectronic circuits. Experience with programming languages such as C++, Python, or Java. Familiarity with testing frameworks like JUnit, PyUnit, or Selenium. Knowledge of version control systems like Git. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment and communicate technical ideas clearly.

Skills/Experience: Proficient in Scan, specializing in ATPG and Pattern verification at Block and Full chip level. Skilled in Scan insertion, ATPG, DRC analysis, Low Coverage Analysis, JTAG and IJTAG. Experienced in scripting for flow automation, using Siemens tools (Tessent), Synopsys tools (DFTMAX, Tetra MAX, VCS, DFT Compiler), Verdi. Familiar with tools: NC-SIM/Irun, Sim-Vision, XCELIUM. Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS and Post-silicon-debug. Hands-on in Perl/Tcl/Python scripting. Excellent analytical, and problem-solving skills. Perform Core and SOC level ATPG to meet Automotive grade quality. Hierarchical ATPG retargeting and Pattern release for application on ATE. Perform SOC and Core level Timing/Non-timing GLS. Silicon bring-up, diagnosis and support for physical failure analysis. Enable Emulation of Gate level SCAN patterns. Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

The DFX Verification Lead position is located in Bangalore and requires 4 to 8 years of experience. The ideal candidate should have a strong understanding of DFT requirements such as Scan, BIST, and JTAG Debuggers. In this role, you will collaborate with IP and integration teams to ensure the successful implementation and verification of design elements. Your responsibilities will include working closely with designers and verification engineers to guarantee functionality and design features for future projects. To excel in this role, you must have a deep knowledge of verification flows and be proficient in debugging at both SoC and system levels. Additionally, expertise in Verilog, System Verilog, or System C for test-bench/model development is required. If you are passionate about chip design and semiconductor projects, we invite you to apply for this exciting opportunity. To express your interest, please submit your resume to krishnaprasath.s@acldgitial.com.,

You should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, encompassing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial to have familiarity with ATPG, Low Value (LV), Built-in self-test (BIST), or Joint Test Action Group (JTAG) tool and flow. Ideally, you should also have experience with a programming language like Perl, along with expertise in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). Proficiency in performance design DFT techniques, understanding of the end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), and the ability to scale DFT would be advantageous. As part of our dynamic team, you will be involved in developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation of products that are cherished by millions globally. Your skills will influence the next wave of hardware experiences, delivering exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team synergizes the best of Google AI, Software, and Hardware to craft profoundly beneficial experiences. We are dedicated to researching, designing, and advancing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to enhance people's lives through technology. Your responsibilities will include collaborating with a team dedicated to Design for Testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks. You will be tasked with crafting Pattern delivery using Automatic Test Pattern Generation (ATPG), engaging in Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns while conducting Silicon data analysis.,

Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys) Must be able to simulate and debug MBIST testbenches. Ability to come up with a detailed test plan based on the Arch specs Should be knowledgeable in all SOC functions such as Digital design, STA, Synthesis, PnR, DV and ATE test. The candidate should have prior experience in managing and developing teams Required Qualification B.E / B.Tech / M.E / M.Tech in Electrical / Electronic Engineering.experience-10-16 years Preferred experience of handling 10+ team members. Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Comfortable with VCS / Verdi and excellent debugging skills Logical in thinking and ability to gel well within a team and be a proactive member of the team. Good communication and leadership skills Excellent team player High Integrity Job Type Full Time Job Location Hubballi

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

TECHNICAL LEAD – DFT SmartSoC is looking for a smart and enterprising leader with expert knowledge in DFT to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking. You will be responsible for leading and managing a team, client communication, and project execution. Job Responsibilities- Lead an internal DFT team, executing projects for an offshore client Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 7+ years of experience in DFT, mainly Scan Architecture, ATPG & MBIST Experience in planning scan chains, running scan insertion flow Experience in latest Cadence tool set Genus & Modus Experience in ATPG for Stuck@, TFT, IDDQ & Path delay faults with tough coverage targets Experience in MBIST architecture, generation and implementation Experience in AECQ100 requirement standard is a big plus Experience in working with a multi-site team is a big plus Experience in working on critical time-bound projects is a big plus Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas