36 Bist Jobs

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We don’t need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 10 - 15 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-HYBRID

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 1-3 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Additional Qualcomm Global CAD Organization is looking for DFT/ATPG Methodology development lead to develop DFTCAD methodologies for Qualcomms 5G products in advanced FinFET semiconductor process nodes. In this role, you will be a member of a global technical team working with SOC Design, DFT, Product and Test, and Diagnostics teams, as well as EDA Tool vendors to develop world-class DFT methodology solutions. Key Responsibilities Lead DFT ATPG flow development, integration, and deployment efforts independently, collaborating with DFT teams, EDA vendors Drive new ATPG methodology, new tool evaluation, design DoEs, both within Qualcomm and partnering with EDA vendors. Develop optimized recipes for improving test quality, reducing test cost, DFT cycle time, pattern simulation runtimes. Qualifications/Experience BE/B.Tech, ME/MTech/MS in Electrical/Electronics/Computer science Engineering 4-6 years demonstrated experience in VLSI EDA/CAD methodology development in areas of DFT, Scan/ATPG Skills Required Strong knowledge of DFT domain specifically on Scan, ATPG and ATPG pattern simulations Strong development skills in TCL, Python Good understanding of SOC DFT Flow, ATE Flow and practices. Familiarity with standard software development process, systems including Configuration Management, QA, Release and Support Ability to plan and execute formal projects, deliverables. Ability to work with multiple WW teams in a fast paced and dynamic environment. Must be a team player, ability to multi-task, with attention to details. Keywords : DFT, ATPG, Scan, VLSI Test, Tessent, TetraMAX, TestMAX, MBIST, SMS

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include, Interface with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 2-6 years experience in ASIC/DFT-simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG -coverage analysis. In depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required ATPG - TestKompress MBIST - Mentor ETVerify Simulation - VCS (preferred), modelsim. Expertise in scripting languages such as Perl, shell, etc. is an added advantage Ability to work in an international team, dynamic environment with good communication skills Ability to learn and adapt to new tools, methodologies.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include , Interfac e with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF) , transition fault (TDF ) models through the use of on-chip test compression techniques. M BIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBI ST verification using unit delay and min/max timing corner s imulations . Work with the P roduct /Test engineering teams on the delivery of manufacturi ng test patterns for ATE . Responsible for supporting post silicon debug effort, issue resolution . Responsible for Diagnostic Tool generation for ATPG , MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 1-6 year s experience in ASIC/DFT - simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG - coverage analysis. In depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required ATPG - TestKompress MBIST - Mentor ETVerify Simulation - VCS (preferred), modelsim . Expertise in scripting languages such as Perl , shell, etc. is an added advantage Ability to work in an international team, dynamic environment with good communication skills Ability to learn and adapt to new tools , methodologies. Ability to do multi-tasking & work on several high priority designs in parallel

Role: DFT Engineer Experience Required: 5-15 Years Location: Bangalore, Hyderabad, Noida, Ahmedabad, and Pune Will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests, and Pattern validation w/wo Timing, DFT mode timing analysis, and sign off. Be responsible for a comprehensive DFT plan Incumbent to work with DFT and cross-functional teams To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field ESSENTIAL SKILLS & EXPERIENCE Strong fundamentals on DFT and ASIC cycle. Sound expertise in Tcl, Perl, and Shell scripting. Technically sound & good team player Hands-on experience with DFT implementation using standard EDA and flow is a must. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Job Details: : Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block. Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. Qualifications: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 7+ years of DFT experience Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Responsibilities: Build and guide a team of DFT engineers to deliver the architecture and the DFT deliveries towards SOC development. Engage with the RTL & physical design program management to plan and execute the DFT deliveries. Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise : At least 10+ years of experience in DFT implementation / methodology Strong understanding of digital design and test principles. Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion Experience with EDA tools , Synopsys and Cadence &scripting languages (e.g., Python, TCL). Knowledge of IC design flows, verification tools, and fault models Ability to identify, analyze, and resolve testing challenges. Work effectively within multidisciplinary teams, communicating complex technical details clearly. Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards. Technically lead/managed 10 - 15 DFT engineers to deliver DFT implementation on SOC Preferred technical and professional experience NA

TECHNICAL LEAD – DFT SmartSoC is looking for a smart and enterprising leader with expert knowledge in DFT to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking. You will be responsible for leading and managing a team, client communication, and project execution. Job Responsibilities- Lead an internal DFT team, executing projects for an offshore client Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 7+ years of experience in DFT, mainly Scan Architecture, ATPG & MBIST Experience in planning scan chains, running scan insertion flow Experience in latest Cadence tool set Genus & Modus Experience in ATPG for Stuck@, TFT, IDDQ & Path delay faults with tough coverage targets Experience in MBIST architecture, generation and implementation Experience in AECQ100 requirement standard is a big plus Experience in working with a multi-site team is a big plus Experience in working on critical time-bound projects is a big plus Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of DFT team, you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in processor flow and post silicon validation

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

About the Role Senior DFT Engineer (4 - 8 Years) | Hyderabad / Bangalore, India Are you passionate about making complex SoCs more testable, robust, and production-ready? As a Senior DFT Engineer , youll play a hands-on role in implementing critical DFT features that ensure silicon success across next-generation ASICs. You will work alongside experienced leads on advanced nodes (14nm and below), contribute to DFT flow development, and implement key test strategies such as scan compression, MBIST, and JTAG. This is your chance to grow into a technical specialist while playing a central role in the silicon lifecyclefrom RTL to tape-out. Key Responsibilities Support DFT architecture implementation and feature insertion for complex SoCs. Implement Scan Insertion , ATPG , Compression , MBIST , and Boundary Scan (JTAG) . Work with Mentor Graphics, Synopsys , or Cadence DFT tools for flow execution and verification. Generate and validate test vectors , support simulation, and ensure fault coverage goals. Assist with DFT verification , timing closure support , and pre-silicon checks . Collaborate with RTL, PD, and STA teams during integration and tape-out phases. Automate DFT flows using Tcl , Perl , or other scripting tools to improve efficiency. Contribute to post-silicon bring-up and production test debugging , where applicable. Work under the guidance of technical leads while also mentoring junior team members when needed. Required Skills & Qualifications Bachelor’s or Master’s degree in Electronics , Electrical Engineering , or a related discipline. 4–8 years of hands-on DFT experience in SoC/ASIC environments. Practical knowledge of: Scan/Compression Insertion and ATPG MBIST architectures and memory BIST flows Boundary Scan (JTAG / IEEE 1149.x) Exposure to silicon bring-up or production test is a strong advantage. Scripting experience using Tcl, Perl , or similar languages. Strong debugging, documentation, and collaboration skills. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

About The Role Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys) Must be able to simulate and debug MBIST testbenches. Ability to come up with a detailed test plan based on the Arch specs Should be knowledgeable in all SOC functions such as Digital design, STA, Synthesis, PnR, DV and ATE test. The candidate should have prior experience in managing and developing teams Required Qualification B.E / B.Tech / M.E / M.Tech in Electrical / Electronic Engineering. experience-10-16 years Preferred experience of handling 10+ team members. Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Comfortable with VCS / Verdi and excellent debugging skills Logical in thinking and ability to gel well within a team and be a proactive member of the team. Good communication and leadership skills Excellent team player High Integrity Job Type Full Time Job Location Hubballi

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the application design and development process Coordinate with stakeholders to gather requirements Ensure project milestones are met Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in application architecture design Knowledge of database management systems Hands-on experience in application testing Additional Information: The candidate should have a minimum of 7.5 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

Required Skills: The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills."

Working closely with a world-class R&D team, you ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM). Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development. Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment. Driving the deployment and smooth execution of SLM solutions into customers projects. Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations. The Impact You Will Have: Enhancing Synopsys Silicon Lifecycle Management (SLM) IP portfolio and end-to-end solution. Driving the adoption of Synopsys SLM solutions at premier customer base worlwide. Influencing the development of next-generation SLM IPs and solutions. What You ll Need: BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field. 4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both. Good knowledge of AXI, APB Background in verification, with at least sub-system level verification Debugging abilities to identify issues in functional verification. Knowledge of DMA, ideally should have verified a sub-system with DMA Knowledge of High-speed IO sub-systems like PCIe and USB A thorough understanding of memory mapping concepts is essential. End to end knowledge of how transactions/data flow between the HSIO interface to/from memory Knowledge and experience with Memory BIST/DFT/ATE/SLT/any other test solutions Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions Customer facing experience is a plus - educating/guiding customer on technical details of a solution Good to have: Hands-on debug experience of silicon is a plus Some programming experience to write/debug simple drivers in C Detailed knowledge of the PCIe and USB protocols Architecture/micro-architecture experience Working with FPGAs

The candidate must have thorough knowledge of DFT basics such as DFT RTL insertion. scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture Proficient in logic design using Verilog Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

We are seeking a passionate and dynamic Lead Engineer Design for Test (DFT) to join our team. If you have extensive expertise in ATPG, SCAN, JTAG, and MBIST, and are eager to lead and mentor a talented team, this is the perfect opportunity for you! Key Responsibilities Lead and guide a team of engineers in the implementation of advanced DFT methodologies. Architect, implement, and validate DFT techniques, including ATPG, SCAN, JTAG, and MBIST, ensuring efficient and scalable design solutions. Collaborate closely with design, verification, and backend teams to deliver high-quality silicon solutions. Drive design reviews, debug issues, and ensure successful tape-out. Optimize and innovate DFT strategies for cutting-edge semiconductor designs. Required Skills and Experience 9+ years of experience in Design for Test (DFT) implementation and methodologies. Strong expertise in ATPG, SCAN, JTAG, MBIST , or at least one DFT technique with hands-on experience. Experience with industry-standard DFT tools such as Synopsys Tetramax, Mentor Tessent, Cadence Modus, or similar tools. Proven ability to debug DFT-related issues in pre-silicon and post-silicon environments. Excellent communication and leadership skills to lead and mentor a team. Proactive and adaptable with a problem-solving mindset. Preferred Qualifications Experience in SOC-level DFT implementation. Familiarity with RTL design and verification methodologies. Knowledge of silicon bring-up and testing processes. Why Join Us? Best Salary in the Market for the right candidate. Attractive bonus plan to reward your contributions. Be part of a fast-growing, innovative team driving next-generation semiconductor solutions. Opportunities to lead and shape projects with cutting-edge technology. A supportive and collaborative work environment that values your expertise and contributions. How to Apply? Please submit your application through prabhu.p@acldigital.com . For any queries, feel free to reach out me

Experience: 5 + - Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPG generation & Simulations along with Pattern Porting/re-targeting and Coverage improvement -Experience with Scan, Compression, ATPG and simulations with Synopsys EDA tools. - Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature - Excellent Customer interaction, Communication and Team work skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Primary responsibilities will include, Interface with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 3-6 yrs of experience is preferred Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Like Requirements: 3 to 6 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG . Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. KEY RESPONSIBILITIES: Define and develop DFT feature verification requirements and test plans for current and next generation products Build comprehensive validation infrastructure including test bench components, agents, monitors, checkers, scoreboards Construct System Verilog and test sequences for comprehensive feature simulation, evaluate feature coverage and regression health Participate in methodology development to increase verification efficiency and effectiveness. PREFERRED EXPERIENCE: 8+ years of VLSI Design and DFT testability Deep understanding of VLSI DFx strategies (ex. JTAG, BIST, ATPG, Boundary Scan) Excellent scripting skills (ex. Perl, C shell, Python). Proficient in debugging RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Strong experience with Verilog, System Verilog, C, and C++ Working knowledge with EDA simulation tools including Synopsys VCS, Cadence NCSIM, Verdi Experience with UVM, OVM or equivalent Experience with formal verification techniques and industry tools Working knowledge of Unix/Linux OS and debug tools Strong analytical skills and attention to detail Excellent written and verbal communication Strong interpersonal skills and proven leadership Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.