Physical Design Engineer

Aritrak Technologies

4 - 9 years

0 - 1 Lacs

bengaluru

Posted:12 hours ago| Platform:

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Skills Required

rtl to gdsii flow pnr physical design tcl synopsys sta cts icc routing perl primetime innovus floor planning drc placement timing closure fc

Work Mode

Work from Office

Job Type

Full Time

Job Description

Roles and Responsibilities:

Perform
RTL-to-GDSII implementation
including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
Work on
P&R flows
using tools such as
Cadence Innovus / Synopsys ICC2
.
Handle
timing analysis and sign-off
using
PrimeTime / Tempus
.
Perform
power planning, IR-drop, and EM analysis
to meet reliability targets.
Execute
DFM closure
DRC/LVS/ANT checks using
Calibre
.
Implement
ECOs
for timing, functionality, and metal fixes.
Work closely with
front-end, verification, and DFT teams
to ensure full-chip integration and timing convergence.
Optimize
Power, Performance, and Area (PPA)
for block- and top-level designs.
Contribute to
flow automation and scripting
using TCL/Perl/Python.
Support
low-power design methodologies (UPF/CPF)
and clock/power gating techniques.
Participate in
design reviews, timing sign-off
, and final GDS tape-out.
Responsible for
block-level and full-chip implementation
on advanced process nodes (7nm/5nm/3nm).

Preferred Tools:

Physical Design:
Cadence Innovus / Synopsys ICC2
STA:
PrimeTime / Tempus
Sign-off:
Calibre, Voltus, RedHawk
Extraction:
StarRC / Quantus
Scripting:
TCL, Perl, Python

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