19 Signoff Jobs

Job Requirements At Quest Global, it's not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better placeto make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Key Responsibilities Key Responsibilities: Delivery Leadership Lead the Define and drive end-to-end RTL-to-GDSII flows, tai...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. To...

As a Physical Design Lead, you will be responsible for overseeing the RTL-to-GDSII flow for advanced technology nodes (7nm and below). Your role will include leading the physical implementation of SoC/IP, driving PPA goals, and ensuring successful tapeouts. You will be managing a team, collaborating with cross-functional groups, and taking ownership of block/top-level execution. Key Responsibilities: - Perform floorplanning, placement, clock tree synthesis (CTS), routing, and signoff - Conduct static timing analysis (STA), handle IR/EM, power & physical verification - Utilize EDA tools such as Innovus, PrimeTime, Calibre, etc. - Proficiency in scripting languages like TCL/Perl/Python, UPF, a...

As a Physical Design Engineer with full chip implementation expertise, including PnR, STA, and signoff flows, your role will involve working on advanced technology nodes and taking ownership from netlist to GDS-II. Key Responsibilities: - Execute full-chip PnR activities from Netlist to GDS-II - Hands-on experience in Floor-planning, Placement, CTS, Routing, Timing Closure (STA) - Perform signoff checks: FEV, VCLP, EMIR, PV - Work on Physical Synthesis through Sign-off GDS2 file generation - Manage signoff convergence, block-level timing signoff, ECO generation, and power signoff - Knowledge of high-performance and low-power implementation methods - Expertise in ICC2 / Fusion Compiler / Inno...

Experience of Place and Route flows using Innovous or Fusion Compiler Experience in Chip Level Design Implementation Experience in IO Ring Design and Analysis Experience in Timing and Design Signoff

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be part of a highly experienced CPU physical design team, responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors. Your role will be crucial in a fast-paced environment with cutting-edge technology. Key Responsibilities: - Own critical CPU units and drive to convergence from RTL-to-GDSII, including synthesis, floor-planning, place and route, timing closure, and signoff. - Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoff...

In your new role you will: Responsible for leading Physical Design and Timing Closure of low-power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design,methodology and process aspects. Enable next generation of place and route engineers via mentoring and thought leadership. You are best equipped for this task if you have: Hands-on experienc...

Role Overview: Job Title : PNR Lead Experience : 8+ Years Work location : Bangalore Job Description: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the de...

Job Title: Physical Design Engineer Experience: 4+ Years Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure. Key Responsibilities: Own block-level or full-chip implementation from RTL to GDSII. Perform: Floorplanning and placement Clock tree synthesis (CTS) Routing and optimization Run and close timing (STA), IR drop, EM, DRC, LVS, and a...

Role: PD Lead Experience: 7+yrs Location: Bangalore Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, ph...

Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Job Description In your new role you will: Responsible for leading Physical Design and Timing Closure of low power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve ...

Role Overview: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be part of the Engineering Group, specifically in the Hardware Engineering team. You will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams to develop solutions and meet performance requirements will be a key aspect of your role. Key Responsibilities: - Lead a team in Bengaluru with 20+ years of CAD/Methodology development experience. - Drive tools, flows, and methodologies globally as part of the worldwide CAD organization. - Develop and implement advanced CAD flows a...

We are looking for a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team in Noida with a hybrid work model where you will be required to work 3 days in the office. As an ideal candidate for this role, you should have a minimum of 6 to 15 years of experience along with strong analytical skills, attention to detail, and the ability to collaborate effectively with cross-functional teams. Proficiency in EDA tools and digital design principles is a must-have for this position. Your key responsibilities will include working closely with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes such as 3nm, 5n...

We are seeking an ASIC RTL Design Lead to join our team in Hyderabad at the earliest. The ideal candidate should possess over 10 years of experience and demonstrate expertise in the following areas: - Proficiency in RTL Design utilizing verilog - Experience in SoC and Subsystem integration, including the integration of peripherals such as PCIE, Ethernet, and USB - Ability to conduct front end flow environment bringup - Strong understanding of Flows, Lint, CDC, Synthesis, Formality, VCLP - Knowledge of tcl or perl scripting - Development of CDC and synthesis constraints, Timing analysis, Signoff If you meet these requirements and are interested in this opportunity, please send your profile to...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experi...

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide...

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. The position available is for a Principal Engi...

As a candidate for this position, you should hold a Bachelor's degree in Computer Science, IT, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in static timing analysis, synthesis, physical design, and automation. It is crucial that you have expertise in physical design tool automation, including synthesis, P&R, and sign-off tools. In addition to the minimum qualifications, preferred qualifications for this role include experience in extracting design parameters, Quality of Results metrics, and analyzing data trends. You should also have knowledge of timing constraints, convergence, and signoff processes, as well as fa...

STA flow setup, convergence, reviews Timing constraint development, analysis, validation and debug Timing, Noise, DRC (transition, capacitance) signoff for multi-mode, multi-corner STA flow optimization Work ondesign automation using TCL/Perl/Python Position Requirements: BTech/MTech degree in Electrical/Electronics with 2-10 years of experience Hands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies (16nm and below). Ability to develop complex timing constraints by working with designers. Should have experience in IP/subsystem/full-chip timing constraints Knowledge of timing commands and constructs supported across synthesis, STA a...