4 Signoff Jobs

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the worlds leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of whats next in electronics and the world. Job Description Location: NOIDA Exp-7-15Y We are seeking a highly skilled & experienced Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope Of Responsibilities As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Synthesis & STA flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in Synthesis & STA domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Bachelor or Master or Ph.D. in Electronics Engineering and specialization in VLSI domain Good understanding of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff Experience with EDA tools like Genus, Fusion Compiler, Primetime, Tempus, Conformal Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can do attitude,?openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industrys leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier . At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make peoples lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark Join Renesas. Lets Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. The position available is for a Principal Engineer/Manager, CAD tools & Methodology based in Noida. The ideal candidate will lead a 20+ CAD team in Noida, delivering tools/flows/methodologies to enable Qualcomm to build its most complex SoCs in cutting-edge process nodes. Responsibilities include managing all CAD functions in Noida, driving tools, flows, methodologies globally, leading the local EDA vendor eco-system, and serving as the interface to Qualcomm execution teams in Noida. Qualifications for this role include at least 15 years of experience in the development of tools/flows/methodologies in RTL, DV, synthesis, PnR, or Signoff. The candidate should have a proven record of driving new innovative tool/flow/methodology solutions and have experience managing a medium-sized team. A preferred educational background is a Masters in VLSI or Computer Science, with a minimum requirement of a Bachelors in Electronics/Electrical Engineering/Computer Science. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodations are needed during the application/hiring process, individuals can reach out to disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. The company expects its employees to abide by all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is only for individuals seeking a job at Qualcomm, and unsolicited submissions from staffing and recruiting agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

As a candidate for this position, you should hold a Bachelor's degree in Computer Science, IT, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in static timing analysis, synthesis, physical design, and automation. It is crucial that you have expertise in physical design tool automation, including synthesis, P&R, and sign-off tools. In addition to the minimum qualifications, preferred qualifications for this role include experience in extracting design parameters, Quality of Results metrics, and analyzing data trends. You should also have knowledge of timing constraints, convergence, and signoff processes, as well as familiarity with parasitic extraction tools and flow. Proficiency in Register-Transfer Level (RTL) languages such as Verilog/SystemVerilog is required, along with a strong understanding of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR), and PDV signoff methodologies. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a key role in innovating products that are beloved by millions worldwide. By leveraging your expertise, you will help shape the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration. In this role, your responsibilities will include driving sign-off timing methodologies for mobile System on a chip (SoCs) to optimize Power Performance Area (PPA) and yield. You will analyze power performance area trade-offs across various methodologies and technologies, as well as work on prototyping subsystems to deliver optimized PPA recipes. Collaboration with cross-functional teams including architecture, Internet Protocols (IPs), design, power, and sign-off methodology is essential. Furthermore, you will engage with foundry partners to enhance signoff methodology for improved convergence and yield.,

STA flow setup, convergence, reviews Timing constraint development, analysis, validation and debug Timing, Noise, DRC (transition, capacitance) signoff for multi-mode, multi-corner STA flow optimization Work ondesign automation using TCL/Perl/Python Position Requirements: BTech/MTech degree in Electrical/Electronics with 2-10 years of experience Hands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies (16nm and below). Ability to develop complex timing constraints by working with designers. Should have experience in IP/subsystem/full-chip timing constraints Knowledge of timing commands and constructs supported across synthesis, STA and PD tools Analysis skills to root cause of timing violations issues and suggest solutions across various stages of design Implementation Strong expertise in Timing ECOs driven by tool and manual ECO techniques for timing closure Sound understanding of Scan/DFT modes and timing Familiar with digital flow design aspects RTL to GDS Proficiency in tcl/perl/python scripts and automation on timing analysis tools Innovate on the flows to resolve timing or DRC issues Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage. Good communication skills in cross-collaborative environment