32 Floorplanning Jobs

Your responsibilities in this role will involve contributing to the development of new product opportunities by assisting with the design, layout, and optimization of Memory/Logic/Analog circuits. You will be responsible for tasks such as parasitic modeling, design validation, reticle experiments, and required tape-out revisions. Additionally, overseeing and managing the layout process including floor-planning, placement, and routing will be part of your role. You will be required to perform verification processes using industry standard simulators and contribute to cross-group communication to drive standardization and group success. Collaborating with various teams such as Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups will be essential to ensure accurate manufacturability of the product. Proactively seeking guidance from Standards, CAD, modeling, and verification groups to enhance design quality will also be a key aspect of your responsibilities. Furthermore, driving innovation into future Memory generations within a dynamic work environment is a crucial part of this role. Micron Technology, Inc. is a global leader in innovative memory and storage solutions, aiming to transform how information is used to enrich life for all. With a strong focus on customers, technology leadership, manufacturing and operational excellence, Micron offers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products under the Micron and Crucial brands. The innovations created by Micron's team enable advancements in artificial intelligence and 5G applications, fueling the data economy from data centers to the intelligent edge and enhancing the client and mobile user experience. To learn more about Micron Technology, Inc., please visit micron.com/careers. If you require assistance with the application process or need reasonable accommodations, please contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and complies with all relevant laws, rules, regulations, and international labor standards. Candidates are encouraged to utilize AI tools to enhance their resumes and application materials. However, all information provided must be accurate and reflect the candidate's genuine skills and experiences. Any misuse of AI to falsify or misrepresent qualifications will lead to immediate disqualification. Micron advises job seekers to be vigilant of unsolicited job offers and verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website.,

As a senior leader in the central physical design team at Marvell, you will shape the long-term vision for physical design capabilities and infrastructure in alignment with the company-wide technology strategy. You will lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS). Your role will involve providing strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs. Mentoring and developing engineering talent will be a key aspect of your responsibilities, fostering a culture of innovation, collaboration, and continuous improvement within the team. You will oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization. Driving cross-functional collaboration with design teams to influence design decisions and ensure successful project execution will also be part of your role. You will navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams. It will be your responsibility to drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality. Managing project schedules, resources, and risks to ensure alignment with business goals and customer requirements will also fall under your purview. Representing the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy will be expected. Collaborating with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies is also a crucial aspect of the role. We are looking for candidates with a Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, along with 18+ years of progressive experience in back-end physical design and verification, including significant leadership roles. A proven track record in leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules is essential. Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges is required. Additionally, familiarity with AI/ML-driven optimization in physical design tools is considered a plus. Strong communication and collaboration skills, along with the ability to influence cross-functional teams and executive stakeholders, are also important qualities for this role. Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness is expected. Marvell offers competitive compensation, great benefits, and a workstyle that promotes shared collaboration, transparency, and inclusivity. The company is dedicated to providing its employees with the tools and resources they need to succeed in meaningful work, grow, and develop within the organization. For more information on working at Marvell, visit our Careers page.,

As a Senior Engineer-High-HBM-Verification at Micron Technology, you will play a crucial role in contributing to the development of new product opportunities by assisting with the design, layout, and optimization of Memory/Logic/Analog circuits. Your responsibilities will involve parasitic modeling, design validation, reticle experiments, and necessary tape-out revisions. You will be responsible for overseeing and managing the layout process, which includes floor-planning, placement, and routing. Additionally, you will perform verification processes using industry standard simulators and contribute to cross-group communication to work towards standardization and group success. Collaboration with various teams such as Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering will be essential to ensure the accurate manufacturability of the product. Seeking guidance from Standards, CAD, modeling, and verification groups to enhance design quality will also be part of your proactive approach. Your role will involve driving innovation into future Memory generations within a dynamic work environment. Micron Technology, Inc. is a global leader in memory and storage solutions, dedicated to transforming how information enriches life for all. With a strong focus on customer satisfaction, technology leadership, and operational excellence, Micron delivers high-performance DRAM, NAND, and NOR memory and storage products through the Micron and Crucial brands. To learn more about Micron Technology, Inc. and explore career opportunities, please visit micron.com/careers. For any assistance with the application process or to request reasonable accommodations, please contact hrsupport_india@micron.com. Micron Technology strictly prohibits the use of child labor and ensures compliance with all relevant laws, rules, regulations, and international labor standards. Join us in our mission to innovate and shape the future of memory technology!,

We are seeking enthusiastic individuals to join our team at Alphawave Semi, where we enable the next generation of digital technology by accelerating critical data communication. As a Physical Design Engineer in our IP Scaling (IPS) organization, you will play a key role in creating customized IP for our expanding customer base, delivering high-speed interconnect solutions for various industries such as High Performance Computing and Artificial Intelligence. Your responsibilities will include driving the backend process through the entire implementation flow, with a focus on floor-planning, power planning, low-power design, place & route optimization, clock tree synthesis, static timing verification, and physical verification. We are looking for someone with at least 5 years of Physical Design experience, a Bachelor's degree in Electrical or Computer Engineering (or equivalent), and advanced technology node experience. Attention to detail, strong collaboration and communication skills, analytical problem-solving abilities, consistency, and self-motivation are essential qualities we seek in our team members. At Alphawave Semi, we offer a flexible work environment that supports personal and professional growth. In addition, we provide a competitive compensation package, Restricted Stock Units (RSUs), opportunities for advanced education from premium institutes, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snacks facility. We are committed to promoting diversity and inclusivity, welcoming applicants of all backgrounds and providing accommodations during the recruitment process. If you are passionate about driving innovation in the world of data communication and are eager to work with a dynamic team of talented individuals, we encourage you to apply for the Physical Design Engineer position at Alphawave Semi.,

Qualcomm India Private Limited is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and driving digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 3+ years of Hardware Engineering experience, or a Master's degree with 2+ years of experience, or a PhD with 1+ year of experience. Key responsibilities include complete ownership of PNR implementation, including Floorplanning, Placement, CTS, post_route, etc., on the latest nodes. Signoff knowledge is mandatory, covering areas such as STA, Power analysis, FV, low power verification, PV, etc. The ideal candidate will possess hands-on experience with Floorplanning, PNR, and STA flows, as well as knowledge of Placement/Clock Tree Synthesis, optimization, and signoff domains like LEC/CLP/PDN. Qualifications for this role include a minimum of 5 years of Hardware Engineering experience or related work experience, along with 5 years of experience with PNR flow in the latest tech nodes (e.g., 4nm/5nm/7nm/10nm). A successful candidate should be a quick learner with strong analytical and problem-solving skills. Qualcomm is an equal opportunity employer committed to providing accessibility for individuals with disabilities during the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Please note that Qualcomm expects its employees to comply with all applicable policies and procedures, including security measures for protecting confidential information. Additionally, individuals seeking a job at Qualcomm should use the official Careers Site, as staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes. For further information about this role, please reach out to Qualcomm Careers.,

Job Summary Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications and Skills Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tapeout. Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floorplanning is a plus. Show more Show less

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understanding of the Physical Verification flow, with experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues primarily using the Calibre tool. Additionally, a deep understanding of ESD, latch-up, etc., is required. You will be responsible for owning and executing Physical Verification activities at the Top/Block level. Collaborating closely with the PD team to address their PV issues and suggest solutions is a key aspect of the role. Working with CAD team to refine existing flows/methodologies and resolve issues is also part of the job scope. Experience in IO, Bump planning, RDL routing Strategy, and developing/implementing timing and logic ECOs are considered advantageous. Knowledge of tools like Innovus/FC for DRC fixing, Python, PERL/TCL scripting, and the ability to plan, work independently, and coordinate with cross-functional teams are essential. Closing sign off DRC based on PNR markers is a plus. The ideal candidate should have experience with physical verification checks such as DRC, LVS, Antenna, ERC, PERC, ESD, etc. Experience with PnR tools like ICC/Innovus and understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre, and ICV is required. A good overall understanding of the Custom IC design flow, layouts, and backend tool flow would be beneficial. Hands-on experience with tools like Innovus/Fusion Compiler, Tech lef is preferable. People management, floorplanning, power planning, and PDN experience are considered a big plus. The ability to script in TCL/PERL and familiarity with physical convergence in PnR tools are also advantageous. In return, we offer a competitive salary, performance-based bonuses, comprehensive benefits package including health insurance, retirement plans, and paid time off. Additionally, you will have opportunities for professional development and career growth in a collaborative and innovative work environment with state-of-the-art facilities.,

As an IO Layout specialist, you will be responsible for designing and verifying GPIO library layouts. Your expertise in floorplanning, placement, IO ring implementation, and IO bus design will be crucial in ensuring the efficient functioning of the layout. With at least 3 years of experience in the field, you will bring valuable insights and knowledge to the team. To excel in this role, you should hold a BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or a related field. Your educational background will provide you with the necessary foundation to tackle the challenges associated with IO layout design. Join us in Bangalore, Hyderabad, or Noida, and be a part of our dynamic team where your skills and experience will contribute to the success of our projects.,

THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field. We are seeking PDN engineers with EMIR and PG planning expertise and a minimum of 4 years of experience. Responsibilities include IR signoff for CPU/high-performance cores, Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP, Development of PG Grid spec for different HM, and validating PG Grid and IR Drops. Additionally, working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations is crucial to enhance PDN Design. The desired skill set includes hands-on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level, proficiency in scripting languages like Tcl and Perl, and familiarity with tools such as Redhawk, Redhawk_SC, Innovus, and Fusion Compiler. The ability to communicate effectively with global cross-functional teams and experience in Power Planning/Floorplanning and Physical Verification is an added advantage. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. Abiding by all applicable policies and procedures, including security requirements, is expected from Qualcomm employees. Please note that our Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through this platform. Unsolicited submissions will not be considered. For more information about this role, please reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a CPU Integration CAD Engineer to join the Engineering Group, specifically in the Hardware Engineering department. As part of the NUVIA team, which is now integrated into Qualcomm, you will be involved in reimagining silicon and developing computing platforms that aim to revolutionize the industry. This role offers the opportunity to collaborate with exceptionally skilled engineers to design innovative solutions that excel in performance, energy efficiency, and scalability. To qualify for this position, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 6 years of experience in Hardware Engineering. Alternatively, a Master's degree with 5+ years of experience or a PhD with 4+ years of experience in a related field will also be considered. The ideal candidate will have 6 to 15 years of experience with a strong academic background. As a CPU Integration CAD Engineer at Qualcomm, you will primarily focus on enabling the floor-planning, physical design, verification, and signoff of Oryon CPU cores. Your responsibilities will include collaborating with global cross-functional teams, developing and implementing flows and methodologies for various design aspects, conducting system tests, recommending improvements, and ensuring the best power, performance, and area outcomes for the silicon products. Preferred qualifications for this role include a Bachelor's or Master's degree in Electrical/Electronics Engineering or Computer Science, extensive experience in high-performance chip development, proficiency in programming languages like Python and TCL, knowledge of data structures and algorithms, automation experience, familiarity with Physical Design tasks, expertise in advanced technology nodes, and proficiency with industry-standard tools such as Siemens/Mentor Calibre and Cadence Innovus. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application and hiring process. The company expects all employees to adhere to relevant policies and procedures, including those related to security and confidentiality. Staffing and recruiting agencies are advised that only individual job seekers should utilize Qualcomm's Careers Site, as unsolicited submissions will not be accepted. For further information about this exciting opportunity, please reach out to Qualcomm Careers for more details.,

THE ROLE: The focus of this role in the AECG ASIC organization is to own physical design implementation for next generation ASICsthat meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICsthat meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to includeFull Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 8+years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: BS or MS degree in in Electrical Engineering or Computer Science. 8years of experience in physical design role leading to an understanding of RTL to GDS development.

THE ROLE: As a PD Manager, you will drive Physical design implementation and execution for next generation SOCs. You will manage PD team for end-to-end PD execution. You will work closely with the SOC architects, Physical design architects/leads, Design leads, IP teams to achieve first-pass silicon success. You will be expected to lead design implementation and convergence activities in the backend from a PnR implementation perspective. The SOCs are based off the most complex process technologies It's a great opportunity to join the talented team that is well-invested in the implementation of futuristic designs in advanced process nodes. THE PERSON: You will be responsible for driving a team of silicon design engineers for the successful delivery of project tape-outs from RTL-GDS. You will use your knowledge of Physical design to lead a complete set of Backend activities, Specifically PnR, timing, verification and signoff including IP integration and full-chip aspects. This position requires a detail-oriented candidate who can drive a larger PD team on solutions across different PD domains. Leader with strong self-driving ability and winning attitude. The person should have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. KEY RESPONSIBILITIES: Lead Physical design team for implementation and convergence of highly complex multi-million gate tiles, subchip and SOC full chip. Responsible for delivery of GDS starting from RTL including Signoff and physical verification. Collaborate with cross-functional teams to drive continuous improvements for achieving better PPA. Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows. Understanding design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle. Collaborate with CAD and EDA vendors to further strengthen AMD and S3 PD closure methodology. Strong interpersonal skills to work across teams in different geographies. Provide technical direction, guidance, and Support to the engineering team. People management, goal setting, assessment, calibration, appraisal and improvement plan. PREFERRED EXPERIENCE: Experienced PD professional with 18+ years of industry experience in managing Physical design execution across RTL to GDSII, PnR, STA, Physical verification, Timing signoff to tapeout. Block-level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification. Well-versed with Physical Design verification signoff techniques such as Formal equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc. Excellent presentation and inter-communication skills. Qualifications : B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering. 15+ years of experience in PD execution. Candidate must have the ability to drive/manage projects from RTL to GDS, with a minimum experience of managing more than 2 SOC tape-outs. Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools.

KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 7+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering

Qualcomm India Private Limited is seeking a Hardware Engineer to join their Engineering Group, specifically focusing on Hardware Engineering. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams to meet performance requirements is a key aspect of this role. Key responsibilities for this position include: - IR Signoff CPU/high performance cores - Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP and other HMs - Development of PG Grid spec for different HM - Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks - Validating the IR Drops using Static IR, Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops - Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design - Good knowledge on PD would is desirable - Proficiency in Python, Perl, TCL The ideal candidate should possess the following qualifications and skills: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field - 4+ years of experience in PDN engineering with EMIR and PG planning expertise - Hands-on experience in PDN Signoff using Redhawk/RHSC/Voltus at block level/SOC Level - Good understanding of Power Integrity Signoff Checks - Proficiency in scripting languages (Tcl and Perl) - Familiarity with Innovus for RDL/Bump Planning/PG eco - Ability to effectively communicate with global cross-functional teams - Experience with tools such as Redhawk, Redhawk_SC, Innovus/Fusion Compiler, Power Planning/Floorplanning, and Physical Verification Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. It is essential for Qualcomm employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised not to use Qualcomm's Careers Site for submissions, as unsolicited applications will not be considered. For more information about this role, please reach out to Qualcomm Careers directly.,

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Collaboration with cross-functional teams including RTL, STA, packaging, and DFT will be essential to successfully handle complex designs on 28nm and below technology nodes. To excel in this role, you must possess strong hands-on experience with tools such as Synopsys/Cadence Innovus, ICC2, Primetime, PT-PX, and Calibre, along with a solid understanding of Physical Design Methodologies including Floorplanning, Placement, CTS, Routing, and STA. Proficiency in timing constraints and closure, Tcl/Tk/Perl scripting, and working with submicron nodes (28nm and below) are also essential skills required for this position. While not mandatory, familiarity with Fusion Compiler, a broader understanding of signal and power integrity, as well as experience in workflow automation and tool scripting would be considered advantageous for this role. If you are excited about the prospect of taking on this challenging and rewarding opportunity, we encourage you to submit your resume to hemanth@neualto.com or spoorthy@neualto.com to express your interest.,

You should have at least 3+ years of relevant experience leading SoC Physical design projects across multiple technology nodes, including 5nm for TSMC and other foundries. Your expertise should include hands-on Place and Route (P&R) skills with in-depth knowledge of ICC/Innovus. You must possess expert knowledge in all phases of Physical Design (PD) from Synthesis to GDSII, with a solid background in Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and strong familiarity with the top level at the latest technology nodes will be beneficial. Collaboration with CAD, Methodology & IP teams is a crucial aspect of PD implementation, necessitating regular sync-ups for deliveries. You should have significant knowledge and preferably hands-on experience in SoC Static Timing Analysis (STA), Power analysis, Physical Verification, and other sign-off processes. Strong problem-solving abilities, a proactive approach, hard work ethic, and excellent interpersonal skills are essential for this role. A Bachelor's Degree in Electrical, Electronics, or Computer Engineering is required. About Company: 7Rays Semiconductor Private Ltd. provides end-to-end custom SoC design solutions, encompassing SoC Architecture, RTL design, Design verification, DFT, Physical Design, and Analog design. Our focus is on serving top semiconductor and system companies to facilitate the design of their complex SoCs. We prioritize building effective partnerships with our clients to deliver high-quality, tailored solutions. With a dedicated engineering team and a proven history of successful project execution, we are dedicated to excellence and innovation in SoC Design, Development, and deployment of customer products.,

The Sr. Staff Physical Design Engineer position at Lattice Semiconductor in Pune, India offers a dynamic opportunity to join the HW design team focused on IP design and full chip integration. As part of a worldwide community of engineers and specialists, you will have the chance to contribute, learn, innovate, and grow within this fast-paced and ambitious organization. Key responsibilities for this role include implementing and leading the RTL to GDSII flow for complex designs, working on various aspects of physical design such as place & route, CTS, routing, floorplanning, powerplanning, timing, and physical signoff. The ideal candidate will have experience in physical design signoff checks, drive efficiency and quality in physical design flow and methodology, collaborate with internal and external teams, and possess scripting knowledge to enhance design efficiency. Additionally, the successful candidate will play a vital role in FPGA design efforts, drive physical design closure of key ASIC blocks & full chip, maintain design quality through quality checks and signoff, develop strong relationships with global teams, mentor colleagues, and may require occasional travel. Requirements for this role include a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent, along with 12+ years of experience in driving physical design activities for ASIC blocks and full chips. Candidates must have multiple tapeout experience and proficiency in industry-standard physical design tools. The ideal candidate should be an independent problem solver, capable of collaborating with diverse groups across different sites and time zones. Lattice Semiconductor values its employees as the cornerstone of its success and offers a comprehensive compensation and benefits program to attract and retain top talent in the industry. As an international developer of low-cost, low-power programmable design solutions, Lattice is committed to customer success and a culture of innovation and achievement. If you thrive in a results-oriented environment, seek individual success within a team-first organization, and are ready to contribute to a collaborative and innovative atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice.,

You should possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, including tasks such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. It is essential to have experience with Physical Design Methodologies and sub-micron technology, particularly in 16nm and lower technology nodes. Moreover, you should have expertise in Analog and Mixed Signal Design and be familiar with handling designs with more than 5M instance count and operating at a frequency of 1.5GHz. Proficiency in programming languages such as Tcl, Tk, and Perl is required to automate the design process and enhance efficiency. Hands-on experience with PnR Suite from Cadence & Synopsys, specifically Innovus & ICC2, is a must. Additionally, you should have a strong background in Static Timing Analysis using tools like PrimeTime for SI analysis, EM/IR-Drop analysis with PT-PX and Redhawk, as well as Physical Verification using Calibre. Understanding the practical application of methodologies, Physical Design Tools, Flow Automation, and driving improvements in these areas is highly beneficial. Experience in complex SOC integration, Low Power and High-Speed Design, as well as proficiency in Advanced Physical Verification Techniques, are desirable skills for this role.,

As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with a minimum of 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience can also be considered. Additionally, candidates with a Bachelor's degree and 2+ years of experience, a Master's degree and 1+ year of experience, or a PhD with relevant experience are eligible. The ideal candidate should possess good hands-on experience in Floorplanning, PNR, and STA flows, as well as knowledge of Placement/Clock Tree Synthesis (CTS) and optimization. Familiarity with signoff domains such as LEC, CLP, and PDN is required, along with proficiency in Unix/Linux, Perl, TCL scripting. Key responsibilities include taking ownership of PNR implementation on the latest nodes, covering tasks like Floorplanning, Placement, CTS, and post-route activities. Signoff knowledge is crucial, encompassing areas like STA, Power analysis, FV, low power verification, and PV. A quick learner with strong analytical and problem-solving skills will excel in this role. Qualifications for this position include a minimum of 15 years of Hardware Engineering experience or related work experience, along with expertise in PNR flow for advanced tech nodes like 4nm, 5nm, 7nm, and beyond.,

You should have at least 3+ years of relevant experience in SoC Physical design, with a focus on multiple technology nodes including 5nm for TSMC and other foundries. Your expertise should include hands-on P&R skills, particularly in ICC/Innovus. You must possess expert knowledge in all aspects of Physical Design (PD) from Synthesis to GDSII, with a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and working at the top level in the latest technology nodes will be highly beneficial. Collaboration with CAD, Methodology & IP teams for PD implementation is critical, requiring regular sync-ups for deliveries. You should have significant knowledge, and preferably hands-on experience, in SoC STA, Power, Physical Verification, and other sign-off processes. Problem-solving capabilities, proactive attitude, hardworking nature, and strong interpersonal skills are essential for this role. A Bachelor's Degree in Electrical, Electronics, or Computer Engineering is required for this position. About Company: 7Rays Semiconductor Private Ltd. provides end-to-end custom SoC design solutions, including SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. The company focuses on offering services to top semiconductor and system companies to assist them in designing complex SoCs. The company believes in building effective partnerships with clients to deliver high-quality solutions tailored to their needs. With a dedicated engineering team and a successful track record in project execution, the company is committed to excellence and innovation in SoC Design, Development, and deployment of customers" products.,

Quest Global is a leading organization known for its innovation and rapid growth in the engineering services sector. With a rich domain expertise and a strong presence in the top OEMs across seven industries, we are a company with a 25-year legacy and a vision to reach a centennial milestone. Driven by ambition, passion, and humility, we are on a journey to shape the future through engineering. We are in search of individuals who embody the spirit of humble geniuses, believing in the power of engineering to turn the impossible into reality. Our ideal candidates are innovators inspired by technology and driven to design, develop, and test solutions as trusted partners for Fortune 500 clients. As a diverse team of engineers, we understand that our work goes beyond technical solutions; we are shaping a brighter future for all. If you are eager to contribute to meaningful projects and be part of an organization that values collective success and learning from failures, we invite you to join us. We are looking for achievers and courageous challenge-crushers who possess the following skills and characteristics: Responsibilities: - Performing floor-planning and routing studies at block and full-chip level - Executing top-level floorplan and clock pushdown to Partition - IO Planning and bump planning - Collaboration with Package team to meet Die file milestones - Conducting full chip and partition level timing analysis - Exploring low power techniques and power reduction opportunities - Designing and analyzing clock distribution - Executing Physical verification activities at full-chip level - Leading technical activities of physical design throughout technology readiness, design, and execution Qualifications: - Proficiency in Netlist2GDSII Implementation, including Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, and Chip finishing - Experience in Physical Design Methodologies and sub-micron technology of 16nm and lower nodes - Handling designs with >1M instance count and 1 GHz frequency - Programming skills in Tcl/Tk/Perl for automating design processes and enhancing efficiency - Hands-on experience with PNR Suite from Cadence & Synopsys (Innovus & ICC2) - Strong background in Static Timing Analysis (PrimeTime SI), EM/IR-Drop analysis (PT-PX, Redhawk), and Physical Verification (Calibre) Education Type: M.E/M.Tech/MS-VLSI Design & Embedded System Job Type: Full Time-Regular Experience Level: Mid Level Total Years of Experience: 5 - 8,

Position Summary Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis, Place and Route, STA, timing and physical signoffs Role and Responsibilities Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Skills and Qualifications Experience in top level floorplanning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through 4+ recent successful SoC tape-outs Should have 8 14 years of experience in physical implementation and design

Lead and execute Analog Mixed-Signal layout design for high-speed DDR/HBM IPs Deliver robust and high-quality physical layout designs ensuring adherence to DDR/HBM specs Apply deep understanding of FinFET and CMOS technology at 28nm and below Handle high-speed digital layout verification with attention to signal integrity Implement advanced floorplanning techniques and apply submicron mitigation strategies Coordinate with remote layout teams globally for layout quality and deliverables Drive internal flow adherence for tape-out readiness and schedule compliance Collaborate with PHY designers, package engineers, and system teams to meet design objectives Oversee IO layout requirements including bondpads, ESD, IR/EM, and DFM considerations Utilize physical verification tools and support Place & Route and top-level verification flows The Impact You Will Have: Shape next-gen high-speed memory interface solutions through expert physical design Ensure quality layout execution in advanced nodes, directly impacting performance and reliability Drive project delivery across global teams with technical leadership and coordination Enable Synopsys to meet customer demand in high-speed memory IPs with quality and timeliness Reinforce design flow adherence and process discipline to ensure tape-out success Contribute to the robustness of global layout practices through review and mentorship What You'll Need: 612 years of experience in Analog Mixed-Signal layout, specifically with DDR/HBM IPs Expertise in FinFET and CMOS layout at 28nm and below Strong knowledge of signal integrity, DRC/LVS/LPE, ESD/latchup, and IO pitch/layout constraints Familiarity with ASIC physical design flows including LEF, Place & Route, and verification Hands-on experience with advanced layout tools and scripting (Perl, TCL, etc. preferred) Proven leadership in global coordination and layout delivery Excellent communication and customer interaction skills