101 Floorplanning Jobs

As a Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams will be essential to develop solutions and meet performance requirements. **Key Responsibilities:** - PNR implementation for Qualcomm SoC's - Hands-on experience on Floorplanning, PNR, and STA flows - Knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc - Understanding of ...

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. Your role will involve working on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - Complete ownership of PNR implementation including Floorplanning, Placement, CTS, post_route, etc on latest nodes. - Signoff knowledge is mandatory, including STA, Power analysis, FV, low po...

You will be a Sr Principal Physical Design Engineer based in Bengaluru, responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on the latest Tech nodes. Your day-to-day tasks will include floorplanning, placement, clock tree synthesis, routing, and physical verification. Additionally, you will collaborate with cross-functional teams, mentor junior engineers, and ensure the design meets performance, power, and area specifications. Key Responsibilities: - Strong expertise in floorplanning, placement, clock tree synthesis, routing, and physical verification - Utilize physical design tools like Cadence Innovus, Syn...

You will be working as a Qualcomm Hardware Engineer at Qualcomm India Private Limited, a leading technology innovator that drives digital transformation to create a smarter, connected future for all. In this role, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaborating with cross-functional teams, you will develop solutions to meet performance requirements. Key Responsibilities: - Demonstrating 8+ years of hands-on experience in different PnR steps such as Floorplanning, Power planning, Placement & Optimization, CTS, Routing, ...

Job Title: Senior Analog Layout Engineer High-Speed Analog Chip (TSMC 5nm) Experience: 8+ Years Location: Remote / India (must support USA/Canada time zone) Travel: Willing to travel to the U.S. for project release (as required) Role Overview We are looking for a Senior Analog Layout Engineer to work on a high-speed analog chip development in advanced TSMC 5nm technology. The candidate will operate as an individual contributor, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision. This role demands deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simula...

About the Role We are looking for a passionate and detail-oriented Physical Design Engineer to join our VLSI design team. The ideal candidate will be responsible for implementing RTL to GDSII, optimizing performance, power, and area, and ensuring high-quality physical designs for advanced semiconductor technologies. Key Responsibilities Perform RTL-to-GDSII flow implementation including synthesis, floorplanning, placement, CTS, routing, and sign-off. Handle timing closure , power optimization , and design rule checks (DRC/LVS) . Work closely with RTL design, verification, and STA teams to meet PPA (Power, Performance, Area) goals. Support EDA tool flow setup , scripting, and automation to im...

As a Physical Design Lead, you will be responsible for overseeing the RTL-to-GDSII flow for advanced technology nodes (7nm and below). Your role will include leading the physical implementation of SoC/IP, driving PPA goals, and ensuring successful tapeouts. You will be managing a team, collaborating with cross-functional groups, and taking ownership of block/top-level execution. Key Responsibilities: - Perform floorplanning, placement, clock tree synthesis (CTS), routing, and signoff - Conduct static timing analysis (STA), handle IR/EM, power & physical verification - Utilize EDA tools such as Innovus, PrimeTime, Calibre, etc. - Proficiency in scripting languages like TCL/Perl/Python, UPF, a...

As an innovative industry leader in memory and storage solutions, Micron Technology is looking for a skilled individual to join our team. Your role will involve contributing to the development of new product opportunities by assisting with the design, layout, and optimization of Memory/Logic/Analog circuits. Your responsibilities will include: - Performing parasitic modeling and assisting in design validation - Overseeing and managing the layout process, including floor-planning and routing - Conducting verification processes with modeling and simulation - Contributing to cross-group communication for standardization and group success - Collaborating with various internal groups to ensure ac...

You have been selected for a role as a Lead in SoC Physical Design at a dynamic company, 7Rays Semiconductor Private Ltd. With over 3 years of relevant experience, your expertise in SoC Physical design across multiple technology nodes, including 5nm for TSMC & Other foundries, will be highly valuable. Your responsibilities will include: - Demonstrating excellent hands-on P&R skills with expert knowledge in ICC/Innovus - Utilizing expert knowledge in all aspects of PD from Synthesis to GDSII - Demonstrating a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure - Experience at taping out multiple chips, especially...

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for independent planning and execution of Netlist-to-GDSII. Your role will involve a good understanding of basics of static timing analysis and well-versed with Block level and SOC level timing closure (STA) methodologies, ECO generation, and predictable convergence. You will collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, and more. Your exposure to high frequency multi-voltage design convergence and good understanding of clock networks will be essential for this role. Additionally, your circuit level comprehension of t...

As a Physical Design Engineer with full chip implementation expertise, including PnR, STA, and signoff flows, your role will involve working on advanced technology nodes and taking ownership from netlist to GDS-II. Key Responsibilities: - Execute full-chip PnR activities from Netlist to GDS-II - Hands-on experience in Floor-planning, Placement, CTS, Routing, Timing Closure (STA) - Perform signoff checks: FEV, VCLP, EMIR, PV - Work on Physical Synthesis through Sign-off GDS2 file generation - Manage signoff convergence, block-level timing signoff, ECO generation, and power signoff - Knowledge of high-performance and low-power implementation methods - Expertise in ICC2 / Fusion Compiler / Inno...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop innovative solutions and meet performance requirements. Key Responsibilities: - Hands-on experience in different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. - Proficiency in high frequency design & advanced tech node implement...

As an experienced SoC Physical design engineer, you should have a minimum of 3+ years of relevant experience leading SoC Physical design projects across multiple technology nodes, including 5nm for TSMC and other foundries. Your expertise should include hands-on Place and Route (P&R) skills with in-depth knowledge of ICC/Innovus. It is essential that you possess expert knowledge in all phases of Physical Design (PD) from Synthesis to GDSII, with a solid background in Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and strong familiarity with the top level at the lat...

Role Overview: As a Sr. Staff Physical Design Engineer at Lattice Semiconductor in Pune, India, you will be part of the HW design team focusing on IP design and full chip integration. Your role involves implementing and leading the RTL to GDSII flow for complex designs, including tasks such as place & route, CTS, routing, floorplanning, powerplanning, and physical signoff. You will also be responsible for driving efficiency and quality in physical design flow, collaborating with internal and external teams, and leveraging scripting knowledge to enhance design efficiency. Key Responsibilities: - Implement and lead the RTL to GDSII flow for complex designs - Work on various aspects of physical...

Back Lead Physical Design Engineer Bangalore, India 10+ Full-Time We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages...

Job Description: Broadcom is looking for a staff level physical design engineer. In this highly visible role, you will be contributing to ASIC for Storage/ AI products. Qualifications: Education and Experience : Master's degree in Electronics/Computer Engineering with over 10 years of experience in physical design. Physical Design Expertise : Extensive experience in Place & Route using Synopsys FC or Cadence Innovus tools is essential. Proficiency in STA using Primetime and/or Tempus. Demonstrated knowledge of Clock Tree Implementation Techniques for High-Speed Design Implementation. Ability to drive front-end and back-end implementation from RTL to GDSII, including synthesis, formal verific...

As a candidate for the position at Micron Technology, your role will involve contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits. You will be responsible for parasitic modeling, design validation, reticle experiments, and tape-out revisions. Additionally, you will oversee and manage the layout process, including floor-planning, placement, and routing. Key Responsibilities: - Contribute to the development of new product opportunities by assisting with design, layout, and optimization of Memory/Logic/Analog circuits - Perform parasitic modeling and assist in design validation, reticle experi...

As a Hardware Engineer at Qualcomm, your main responsibility will be to plan, design, optimize, verify, and test electronic systems, including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. It is crucial to collaborate with cross-functional teams to meet performance requirements and deliver innovative solutions. Key Responsibilities: - Take ownership of PNR implementation on the latest nodes, covering tasks like Floorplanning, Placement, CTS, and post-route activities. - Possess signoff knowledge including STA, Power analysis, FV, low power verification, and PV. - Utilize hands...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - Complete ownership of PNR implementation including Floorplanning, Placement, CTS, post_route, etc on the latest nodes - Signoff knowledge is mandatory (STA, Power analysis, FV, low power verification, PV, etc) - Q...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis (CTS), formal verification, physical verification (DRC/LVS), power delivery network (PDN), timing closure, and power optimization. Your role will involve making PPA trade-off decisions for critical cores, ensuring timing convergence of high-frequency data-path intensive cores, and implementing advanced STA concepts. You will work on block-level PnR convergence using tools like Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. Additio...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be part of a highly experienced CPU physical design team, responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors. Your role will be crucial in a fast-paced environment with cutting-edge technology. Key Responsibilities: - Own critical CPU units and drive to convergence from RTL-to-GDSII, including synthesis, floor-planning, place and route, timing closure, and signoff. - Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoff...

Key Responsibilities Lead STA and PNR efforts for large, multi-interface, or mixed-signal subsystems Develop and refine STA and PNR methodologies tailored to complex subsystem challenges Drive automation and validation of timing and physical design data across subsystem boundaries Mentor and guide junior engineers, fostering technical growth and knowledge sharing Collaborate cross-functionally to resolve design, timing, and physical implementation challenges Present technical solutions and lead discussions with internal teams and customers on subsystem-level trade-offs and integration

Key Responsibilities Lead block-level PNR from floorplanning through routing, ensuring implementation meets timing, power, and area targets Design robust power grids and implement EM/IR-aware routing for block-level power integrity Work closely with timing engineers to resolve PPA bottlenecks affecting timing and signal integrity Manage and optimize physical verification including DRC, LVS, antenna checks, and physical signoff Automate PNR flows using scripting to enhance productivity and design quality Mentor junior engineers and promote best practices in physical design methodology Coordinate with RTL, STA, verification, and backend integration teams for block-to-chip integration

Location: Hybrid Job Type: Full-Time Posted Date: 6/30/2025 About The Role Job Overview: We are seeking a Senior Physical Design Engineer with strong expertise in Netlist-to-GDSII implementation and experience working on advanced submicron technology nodes. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes. Key Responsibilities: ? Drive full Netlist-to-GDSII flow: floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. ? Perform Static Timing Analysis (STA) and ensure timing closure across all design corners. ? Execute power integrity and physical verification checks (LVS, DRC). ? Co...

Senior Physical Design Engineer Physical Design >> Senior Physical Design Engineer Post Senior Physical Design Engineer Required Experience 5 to 10 Years Location: Delhi NCR, Bangalore, Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Physical Design Engineer knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI) Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc) Should have worked extensively on XTalk/SI/EM Knowledge about CTS, Clock tree methodology and clock skewing. Tool specific knowledge: ICC, innovus, primetim...