59 Floorplanning Jobs

As a member of the Micron Technology team, you will play a crucial role in contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits. Your responsibilities will also include parasitic modeling, design validation, reticle experiments, and required tape-out revisions. You will oversee and manage the layout process, including floor-planning, placement, and routing, while performing verification processes with modeling and simulation using industry standard simulators. Your role will involve contributing to cross-group communication to work towards standardization and group success. Additionally, yo...

As a Hardware Engineer at Qualcomm India Private Limited, you will play a vital role in planning, designing, optimizing, verifying, and testing electronic systems that contribute to the launch of cutting-edge, world-class products. Your responsibilities will encompass working on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements. **Key Responsibilities:** - Complete ownership of PNR implementation including Floorplanning, Placement, Clock Tree Synthesis (CTS), post_route, etc. on latest nodes. - Mandatory signoff knowl...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - 8-10 years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure - ...

As a CPU Physical Design Lead at 7Rays Semiconductors, you will be responsible for the development of high-speed cores such as CPU, GPU, and DDR. With over 10 years of experience, you must possess significant knowledge in synthesis, constraints, and physical design, keeping power, performance, and area (PPA) in mind throughout the process. Collaboration with RTL designers for optimizations and feedback will be a key part of your role, ensuring efficient floorplanning for multi-core, L2 & L3, and power planning up to Bumps. Your expertise in silicon margins, VT trade-off, power, and area impact will be vital in making informed decisions. Understanding critical paths, pipelining, latency, and ...

About the Role: You will be part of Incise Infotech Limited's expanding VLSI Design team, focusing on Static Timing Analysis (STA) for high-performance chip design projects. This role is suited for individuals with a strong passion for full-chip timing closure, constraint development, and timing verification in advanced technology nodes. Key Responsibilities: - Performing Static Timing Analysis at block and full-chip levels using tools like PrimeTime or Tempus. - Identifying and resolving setup, hold, transition, and other timing violations. - Collaborating closely with RTL, Synthesis, and Physical Design teams to achieve timing closure. - Developing, validating, and managing SDC constraints...

The role at Ceremorphic AI hardware involves owning and driving the physical implementation of next-generation SOCs. The responsibilities include understanding requirements, defining physical implementation methodologies, collaborating with various teams, implementing and verifying designs, interacting with foundry, and supervising resource allocation and scheduling. The ideal candidate should have hands-on expertise in floorplanning, power planning, logic and clock tree synthesis, placement, timing closure, routing, extraction, physical verification (DRC & LVS), crosstalk analysis, and EM/IR. Additionally, full chip/top-level expertise in multiple chip tape-outs, understanding of SCAN, BIST...

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible in order to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be con...

Physical Design Lead (7-10 years experience) Company: HCL Tech Job Summary: We are looking for a highly motivated and experienced Physical Design Lead to join our dynamic team and play a vital role in the physical design and implementation of next-generation integrated circuits (ICs). This leadership role offers the opportunity to leverage your expertise in physical design methodologies and lead a team in achieving successful tapeouts. Responsibilities: Leadership: Lead and manage a team of physical design engineers, fostering a collaborative and high-performing work environment Delegate tasks, provide technical guidance, and mentor junior engineers to ensure their professional development M...

As a Physical Design Engineer based in Bangalore, India with over 3 years of experience, you will be responsible for various aspects of physical design for SoC using Innovus. Your key responsibilities will include floorplanning, IO ring creation, understanding ESD and latch-up requirements for foundry, and implementation strategies for placement. You will need to demonstrate expertise in hierarchical design implementation, including partitioning, push down methodologies, core/tile PG creation, and knowledge of analog components placement based on design specifications. Additionally, RDL knowledge and experience working with packaging are essential for SoC floorplan design. A critical aspect ...

Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling differen...

Physical Implementation activities for Sub systems include Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. You should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Your expertise should include timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. You should be well-versed with Block level PnR convergence using Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. A good understanding of clocking architecture is essential. Collaboration with design, DFT, and PNR tea...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group, specifically in the Hardware Engineering department. As a Qualcomm Hardware Engineer, you will be at the forefront of technology innovation, contributing to the development of cutting-edge products that drive digital transformation and enable next-generation experiences. Your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. To qualify for this role, you should hold a Bachelor's degree, Master's degree, or PhD in Comp...

Your role at Micron Technology as a SR ENG-HIG-HBM-VERIFICATION will involve contributing to the development of new product opportunities by assisting with the design, layout, and optimization of Memory/Logic/Analog circuits. You will be responsible for parasitic modeling, design validation, reticle experiments, tape-out revisions, and overseeing the layout process including floor-planning, placement, and routing. Additionally, you will perform verification processes with modeling and simulation using industry standard simulators. Collaboration is key in this role, as you will contribute to cross group communication to work towards standardization and group success. You will liaise with vari...

As a High-Speed Analog Layout Engineer at our company, you will be responsible for designing and implementing high-speed analog and mixed-signal layouts, focusing on advanced FinFET nodes such as TSMC 2nm, 3nm, 5nm, and 7nm. With your 3+ years of experience in this field, you will play a crucial role in ensuring the success of our projects. Your main responsibilities will include: - Creating custom layouts for high-speed IPs like PLLs, SERDES, clock buffers, and data paths, utilizing your strong hands-on experience in this area. - Utilizing tools such as Cadence Virtuoso, Calibre DRC/LVS, and PEX flows to ensure accurate and efficient layout designs. - Demonstrating a proven track record of ...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or ...

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required...

Qualcomm India Private Limited is a leading technology innovator that enables next-generation experiences and drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electr...

Job Description : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimiza...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Hardware Engineer at Qualcomm, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to ensure solutions meet performance requirements. To be considered for this role, you must have a Bachelor's degree in Computer Science, Electrical/Electro...

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvells custom Processor/ASIC solution offers a differentiated ...

Back Lead Physical Design Engineer Bangalore, India 10+ Full-Time We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages...

Your role at Micron Technology will involve contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits. You will be responsible for parasitic modeling, design validation, reticle experiments, and tape-out revisions. Additionally, you will oversee the layout process, including floor-planning, placement, and routing. As part of your responsibilities, you will perform verification processes using industry standard simulators and contribute to cross-group communication to work towards standardization and group success. Collaboration with various teams such as Marketing, Probe, Assembly, Test, Process...

Your role at Micron Technology will involve contributing to the development of new product opportunities by assisting with the design, layout, and optimization of Memory/Logic/Analog circuits. This will include tasks such as parasitic modeling, design validation, reticle experiments, and overseeing the layout process, including floor-planning, placement, and routing. You will also be responsible for performing verification processes using industry standard simulators, and collaborating with various groups to ensure successful manufacturability of the product. Your role will require active participation in cross-group communication to work towards standardization and group success. This will ...

Your role at Micron Technology will involve contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits. You will be responsible for parasitic modeling, design validation, reticle experiments, and required tape-out revisions. Additionally, you will oversee and manage the layout process including floor-planning, placement, and routing, while performing verification processes with modeling and simulation using industry standard simulators. You will also play a key role in cross group communication to work towards standardization and group success. Collaborating with Marketing, Probe, Assembly, Test,...

You will be contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits. This includes parasitic modeling, design validation, reticle experiments, and required tape-out revisions. You will be overseeing and managing the layout process, which includes floor-planning, placement, and routing. Additionally, you will be performing verification processes with modeling and simulation using industry standard simulators. Your role will also involve contributing to cross-group communication to work towards standardization and group success. You will collaborate with Marketing, Probe, Assembly, Test, Process...