11 Floorplanning Jobs

Position Summary Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis, Place and Route, STA, timing and physical signoffs Role and Responsibilities Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Skills and Qualifications Experience in top level floorplanning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through 4+ recent successful SoC tape-outs Should have 8 14 years of experience in physical implementation and design

Lead and execute Analog Mixed-Signal layout design for high-speed DDR/HBM IPs Deliver robust and high-quality physical layout designs ensuring adherence to DDR/HBM specs Apply deep understanding of FinFET and CMOS technology at 28nm and below Handle high-speed digital layout verification with attention to signal integrity Implement advanced floorplanning techniques and apply submicron mitigation strategies Coordinate with remote layout teams globally for layout quality and deliverables Drive internal flow adherence for tape-out readiness and schedule compliance Collaborate with PHY designers, package engineers, and system teams to meet design objectives Oversee IO layout requirements including bondpads, ESD, IR/EM, and DFM considerations Utilize physical verification tools and support Place & Route and top-level verification flows The Impact You Will Have: Shape next-gen high-speed memory interface solutions through expert physical design Ensure quality layout execution in advanced nodes, directly impacting performance and reliability Drive project delivery across global teams with technical leadership and coordination Enable Synopsys to meet customer demand in high-speed memory IPs with quality and timeliness Reinforce design flow adherence and process discipline to ensure tape-out success Contribute to the robustness of global layout practices through review and mentorship What You'll Need: 612 years of experience in Analog Mixed-Signal layout, specifically with DDR/HBM IPs Expertise in FinFET and CMOS layout at 28nm and below Strong knowledge of signal integrity, DRC/LVS/LPE, ESD/latchup, and IO pitch/layout constraints Familiarity with ASIC physical design flows including LEF, Place & Route, and verification Hands-on experience with advanced layout tools and scripting (Perl, TCL, etc. preferred) Proven leadership in global coordination and layout delivery Excellent communication and customer interaction skills

Lead and execute Analog Mixed-Signal layout design for high-speed DDR/HBM IPs Deliver robust and high-quality physical layout designs ensuring adherence to DDR/HBM specs Apply deep understanding of FinFET and CMOS technology at 28nm and below Handle high-speed digital layout verification with attention to signal integrity Implement advanced floorplanning techniques and apply submicron mitigation strategies Coordinate with remote layout teams globally for layout quality and deliverables Drive internal flow adherence for tape-out readiness and schedule compliance Collaborate with PHY designers, package engineers, and system teams to meet design objectives Oversee IO layout requirements including bondpads, ESD, IR/EM, and DFM considerations Utilize physical verification tools and support Place & Route and top-level verification flows The Impact You Will Have: Shape next-gen high-speed memory interface solutions through expert physical design Ensure quality layout execution in advanced nodes, directly impacting performance and reliability Drive project delivery across global teams with technical leadership and coordination Enable Synopsys to meet customer demand in high-speed memory IPs with quality and timeliness Reinforce design flow adherence and process discipline to ensure tape-out success Contribute to the robustness of global layout practices through review and mentorship What You'll Need: 612 years of experience in Analog Mixed-Signal layout, specifically with DDR/HBM IPs Expertise in FinFET and CMOS layout at 28nm and below Strong knowledge of signal integrity, DRC/LVS/LPE, ESD/latchup, and IO pitch/layout constraints Familiarity with ASIC physical design flows including LEF, Place & Route, and verification Hands-on experience with advanced layout tools and scripting (Perl, TCL, etc. preferred) Proven leadership in global coordination and layout delivery Excellent communication and customer interaction skills

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Creating floorplans, routing, and performing physical verifications to meet quality standards. Debugging and solving complex layout issues to ensure high-quality deliverables. Collaborating with design engineers to optimize layout for performance, power, and area. Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. Ensuring compliance with DRC, LVS, ERC, and antenna rules. The Impact You Will Have: Contribute to the development of cutting-edge technologies that drive the Era of Smart Everything. Enhance the performance and reliability of next-generation semiconductor IPs. Accelerate the time-to-market for high-performance silicon chips. Reduce risks associated with layout design by adhering to stringent verification requirements. Foster a collaborative and innovative work environment. Support Synopsys mission to lead in chip design and software security. What You'll Need: BTech/MTech in Electrical Engineering or related field. 2+ years of relevant experience in analog layout design. Proficiency in developing quality layouts and performing physical verifications. In-depth understanding of deep submicron effects and floorplan techniques. Experience with CMOS, FinFET, and GAA process technologies at 7nm and below. Knowledge of layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floorplanning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-market for differentiated products. Driving innovation in semiconductor technology and design. Contributing to the success of Synopsys Silicon IP business. Fostering a collaborative and inclusive work environment. What You'll Need: BTech/MTech degree in a relevant field. 4+ years of experience in analog layout design. Proven track record in developing high-quality layouts and meeting verification timelines. Strong understanding of deep submicron effects and floorplan techniques. Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation.

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floor planning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-market for differentiated products. Driving innovation in semiconductor technology and design. Contributing to the success of Synopsys Silicon IP business. Fostering a collaborative and inclusive work environment. What You'll Need: BTech/MTech degree in a relevant field. 4+ years of experience in analog layout design. Proven track record in developing high-quality layouts and meeting verification timelines. Strong understanding of deep submicron effects and floorplan techniques. Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation.

Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelor s degree with at least 1-3 years of design/EDA experience or Master s degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred. Good programming knowledge in Unix, Shell scripting, perl and importantly TCL Strong customer-facing communication and problem solving skills Strong personal drive for continuous learning and expanding professional skill sets Excellent verbal and written communication skills Familiar with EDA tool operation, setup and debug: Digital: Genus, Innovus, Tempus, Voltus, etc

Description We are seeking a highly skilled ASIC Physical Design, Sr Staff Engineer to join our team in India. In this role, you will be responsible for the physical design and implementation of high-performance ASICs, collaborating closely with cross-functional teams to ensure successful project delivery. Responsibilities Design and implement physical layouts for ASIC designs. Conduct place and route activities to meet timing and area requirements. Perform timing analysis and optimization to ensure high-performance ASICs. Collaborate with RTL designers to ensure design feasibility and manufacturability. Utilize EDA tools for physical design tasks such as Cadence, Synopsys, or Mentor Graphics. Conduct DRC/LVS checks and ensure design compliance with specifications. Support the verification team in physical design verification activities. Participate in design reviews and provide feedback for design improvements. Skills and Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 2-7 years of experience in ASIC physical design or related roles. Strong knowledge of ASIC design flow and methodologies. Proficiency in using EDA tools for physical design (e.g., Cadence, Synopsys, Mentor Graphics). Experience with place and route, timing closure, DRC/LVS checks, and physical verification. Familiarity with scripting languages (e.g., Perl, Tcl, Python) for automation of design tasks. Understanding of semiconductor manufacturing processes and design for manufacturability (DFM). Strong problem-solving skills and attention to detail.

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 6+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 6+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

We are seeking an Analog Layout Engineer 3-8 for designing PMIC, converters, high-speed clocking circuits, and analog modules in FinFET, CMOS, and BiCMOS/BCD technologies Strong skills in layout, parasitic extraction, and verification tools required. Perks and benefits Competitive Salary Referral program Insurance