101 Floorplanning Jobs - Page 2

As a Physical Design Engineer, you will be responsible for the physical design of ASICs. This includes tasks such as floorplanning, clock tree synthesis, placement, routing, timing closure, and physical verification. Your contributions will be crucial to the successful tape out cycles of multiple chips, ensuring the efficiency of the PD life cycle and ECO life cycle. Your expertise in clock-tree synthesis and power-aware PD flows, such as ADM, P&R, will be essential for the project's success. Additionally, your familiarity with PD-STA, timing constraints, and multi-mode, multi-corner timing closure will play a key role in achieving project milestones. **Qualifications Required:** - 3+ years ...

As a Staff Engineer - Analog Design at Micron Technology, your role will involve the following key responsibilities: - Design, implement, and integrate complex analog circuits including CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products. - Design, implement, and integrate synchronous and asynchronous custom digital blocks. - Contribute to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits. - Conduct parasitic modeling and design validation, reticle experiments, and require...

Skills requried: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes. Should have experience in Analog and Mixed Signal Design Should have experience in handling >5M instance count , 1.5GHz frequency designs. Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience on Static T...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing, and physical verification. The role also involves collaborating with cross-functional teams, mentoring junior engineers, and ensuring design meets performance, power, and area specifications. Qualifications Strong expertise in flo...

As a High-Speed Analog Layout Engineer at our company, you will be responsible for designing high-speed analog and mixed-signal layouts, focusing on advanced FinFET nodes such as TSMC 2nm, 3nm, 5nm, and 7nm. Your role will require you to have a strong background in custom layout for high-speed IPs like PLLs, SERDES, clock buffers, and data paths. Key Responsibilities: - Hands-on experience in custom layout for high-speed IPs including PLLs, SERDES, clock buffers, and data paths - Proficiency in tools like Cadence Virtuoso, Calibre DRC/LVS, and PEX flows - Demonstrated track record of delivering clean layouts with successful DRC/LVS/EM/IR sign-offs through multiple tapeouts - Expertise in lay...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity ...

Job Description: You will be responsible for designing and verifying GPIO library layouts. Your expertise in floorplanning, placement, IO ring implementation, and IO Bus design will be crucial for this role. Key Responsibilities: - Design and verify Layouts for GPIO library - Perform floorplanning and placement activities - Implement IO ring and IO Bus designs Qualifications Required: - BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field - Minimum 3+ years of experience in Layout design and verification of GPIO library,

As a Qualcomm Hardware Engineer, your role involves planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities: - Complete ownership of PNR implementation including Floorplanning, Placement, CTS, and post_route on the latest nodes - Mandatory signoff knowledge including STA, Power analysis, FV, low power verification, PV, etc - Quick learner with good analytical and problem-solving skills Qualifications Required: - Bachelor's degree in Computer Sc...

As a Memory Layout Lead at our company, you will play a crucial role in driving the physical design and delivery of high-performance, low-power, and high-density semiconductor memory IPs including SRAM, ROM, register files, CAMs, and more. Your main responsibility will be to lead the end-to-end layout design and floorplanning for advanced-node memory IPs. Additionally, you will collaborate with circuit, CAD, and SoC integration teams to ensure optimal implementation. Your innovative layout techniques will be essential in achieving competitive density and performance targets. You will also be responsible for providing comprehensive IP deliverables such as GDSII, LEF, Liberty (.lib), Verilog m...

As a member of the Micron Technology team, you will play a vital role in contributing to the development of new product opportunities and ensuring the successful design and optimization of Circuits of Analog/Digital/Memory. Your responsibilities will include: - Assisting with the overall design, layout, and optimization of Circuits - Conducting parasitic modeling and participating in design validation activities - Overseeing the layout process, including floor-planning, placement, and routing - Performing verification processes using industry standard simulators - Collaborating with various groups such as Marketing, Probe, Assembly, Test, and Product Engineering to ensure manufacturability o...

As a Physical Verification Engineer for SOC/blocks, your role involves performing physical verification for SOCs, cores, and blocks, which includes tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. You will be responsible for addressing critical design and execution challenges related to physical verification and sign-off. It is essential for you to have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Collaboration with PNR engineers to achieve sign-off at various stages of the design process is also a key aspect of your role. Your qualifications and skills should include proficiency in physical verification for SoC/full-chip and b...

Physical Design and Timing closure of Infineon SoCs targeted for IoT and MCU markets. Job Description In your new role you will: This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Candidate will be responsible to drive die area, performance, power goals for hierarchical blocks/Top. Candidate will work on various stages of physical design implementation which includes floorplanning, IO planning, packager co-design, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IRdrop, physical verification checks. Candidate is expected to have deep understanding and hands-on experience in implementing ...

As the candidate for the position at Ceremorphic AI hardware, you will be responsible for owning and driving the physical implementation of next-generation SOCs. Your role will involve understanding requirements and defining physical implementation methodologies. You will collaborate with architecture, design, front end, and CAD teams to ensure the delivery of high-quality physical designs. Additionally, you will be responsible for implementing and verifying designs at all levels of hierarchy in the SOC. Your role will also entail interacting with the foundry on matters related to technology, schedule, and signoff, as well as supervising resource allocation and scheduling. Key Responsibiliti...

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. Your role will involve working on a variety of systems including yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to develop solutions and meet performance requirements. Key Responsibilities: - Take complete ownership of PNR implementation including Floorplanning, Placement, CTS, post_route, etc, on the latest nodes - Demonstrate signoff knowledge in areas such as STA...

You have a job opportunity for the Manager / Senior Role Physical Design Engineer position in Hyderabad. Your primary responsibilities will include: - Performing IP/Block level PnR activities from Netlist to GDS-II - Demonstrating good knowledge of all PnR activities such as Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Executing all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handling signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Having knowledge of high performance and low power implementation methods (preferred) - Expertise in ICC2/Fusion Compil...

You should have at least 3+ years of relevant experience in SoC Physical design, with a focus on multiple technology nodes including 5nm for TSMC and other foundries. Your expertise should include hands-on P&R skills, particularly in ICC/Innovus. You must possess expert knowledge in all aspects of Physical Design (PD) from Synthesis to GDSII, with a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. - Experience in taping out multiple chips and working at the top level in the latest technology nodes will be highly beneficial. - Collaboration with CAD, Methodology & IP teams for PD implementation is critical, r...

Role Overview: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. This position will focus on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with an emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. Key Responsibilities: - Drive floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA - Engage in cross-fun...

As a member of the Micron Technology team, you will play a crucial role in contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits. Your responsibilities will also include parasitic modeling, design validation, reticle experiments, and required tape-out revisions. You will oversee and manage the layout process, including floor-planning, placement, and routing, while performing verification processes with modeling and simulation using industry standard simulators. Your role will involve contributing to cross-group communication to work towards standardization and group success. Additionally, yo...

As a Hardware Engineer at Qualcomm India Private Limited, you will play a vital role in planning, designing, optimizing, verifying, and testing electronic systems that contribute to the launch of cutting-edge, world-class products. Your responsibilities will encompass working on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements. **Key Responsibilities:** - Complete ownership of PNR implementation including Floorplanning, Placement, Clock Tree Synthesis (CTS), post_route, etc. on latest nodes. - Mandatory signoff knowl...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - 8-10 years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure - ...

As a CPU Physical Design Lead at 7Rays Semiconductors, you will be responsible for the development of high-speed cores such as CPU, GPU, and DDR. With over 10 years of experience, you must possess significant knowledge in synthesis, constraints, and physical design, keeping power, performance, and area (PPA) in mind throughout the process. Collaboration with RTL designers for optimizations and feedback will be a key part of your role, ensuring efficient floorplanning for multi-core, L2 & L3, and power planning up to Bumps. Your expertise in silicon margins, VT trade-off, power, and area impact will be vital in making informed decisions. Understanding critical paths, pipelining, latency, and ...

About the Role: You will be part of Incise Infotech Limited's expanding VLSI Design team, focusing on Static Timing Analysis (STA) for high-performance chip design projects. This role is suited for individuals with a strong passion for full-chip timing closure, constraint development, and timing verification in advanced technology nodes. Key Responsibilities: - Performing Static Timing Analysis at block and full-chip levels using tools like PrimeTime or Tempus. - Identifying and resolving setup, hold, transition, and other timing violations. - Collaborating closely with RTL, Synthesis, and Physical Design teams to achieve timing closure. - Developing, validating, and managing SDC constraints...

The role at Ceremorphic AI hardware involves owning and driving the physical implementation of next-generation SOCs. The responsibilities include understanding requirements, defining physical implementation methodologies, collaborating with various teams, implementing and verifying designs, interacting with foundry, and supervising resource allocation and scheduling. The ideal candidate should have hands-on expertise in floorplanning, power planning, logic and clock tree synthesis, placement, timing closure, routing, extraction, physical verification (DRC & LVS), crosstalk analysis, and EM/IR. Additionally, full chip/top-level expertise in multiple chip tape-outs, understanding of SCAN, BIST...

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible in order to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be con...

Physical Design Lead (7-10 years experience) Company: HCL Tech Job Summary: We are looking for a highly motivated and experienced Physical Design Lead to join our dynamic team and play a vital role in the physical design and implementation of next-generation integrated circuits (ICs). This leadership role offers the opportunity to leverage your expertise in physical design methodologies and lead a team in achieving successful tapeouts. Responsibilities: Leadership: Lead and manage a team of physical design engineers, fostering a collaborative and high-performing work environment Delegate tasks, provide technical guidance, and mentor junior engineers to ensure their professional development M...