Jobs
Interviews

Cadence System Design and Analysis

2 Job openings at Cadence System Design and Analysis
VIP Development and Verification Engineer (EDA) Noida,Uttar Pradesh,India 2 years None Not disclosed On-site Full Time

Job Summary We are seeking a highly motivated candidate with expertise in functional verification, specifically focusing on Verification IP (VIP) development. The ideal candidate will be able to quickly and independently adapt to new technologies and protocols. Excellent communication skills are essential, as the role involves cross-functional collaboration and close interaction with customers. Job Responsibilities Responsible for the design, development, verification and deployment of the VIP. Experience and Technical Skills required 2 to 5 years of domain experience Proficiency in functional verification, test environment creation using SV/UVM with strong debug skills. Hands-on knowledge of C/C++/Scripting. Working experience on layered Protocols - UCIe, PCIe, CXL, Ethernet. Prior VIP usage and development experience is a plus. Strong Digital Electronics and Programming fundamentals. Self-motivated individuals with strong analytical and communication skills. Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics

Principal Verification Design Engineer pune,maharashtra,india 0 years None Not disclosed On-site Full Time

Job Description Design and lead high speed IP (USB3, PCIE, DPHY etc) development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development – analog design, layout, digital design, documentation and silicon validation. Would be required to participate in customer facing discussions. Requirements B.Tech/BE/ME/Mtech Exp - 5 +yrs • Hands on design experience in various analog IP like PLLs, data converters, serial interfaces etc. • Must have participated in full cycles of analog IP creation – right from spec to silicon debug and char • Must have good communication skills and should be team player. • Working experience in PHY (PCIE, USB2, USB3) development is desired