Job Summary We are seeking a highly motivated candidate with expertise in functional verification, specifically focusing on Verification IP (VIP) development. The ideal candidate will be able to quickly and independently adapt to new technologies and protocols. Excellent communication skills are essential, as the role involves cross-functional collaboration and close interaction with customers. Job Responsibilities Responsible for the design, development, verification and deployment of the VIP. Experience and Technical Skills required 2 to 5 years of domain experience Proficiency in functional verification, test environment creation using SV/UVM with strong debug skills. Hands-on knowledge of C/C++/Scripting. Working experience on layered Protocols - UCIe, PCIe, CXL, Ethernet. Prior VIP usage and development experience is a plus. Strong Digital Electronics and Programming fundamentals. Self-motivated individuals with strong analytical and communication skills. Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics
Job Description Design and lead high speed IP (USB3, PCIE, DPHY etc) development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development – analog design, layout, digital design, documentation and silicon validation. Would be required to participate in customer facing discussions. Requirements B.Tech/BE/ME/Mtech Exp - 5 +yrs • Hands on design experience in various analog IP like PLLs, data converters, serial interfaces etc. • Must have participated in full cycles of analog IP creation – right from spec to silicon debug and char • Must have good communication skills and should be team player. • Working experience in PHY (PCIE, USB2, USB3) development is desired
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary: A passionate and motivated CM automation engineer to support the Palladium emulation product line. We offer amazing opportunities to grow, no matter where you are in your career. This position involves managing daily software build, test, and configuration management support for other cross functional teams. The responsibility also includes maintaining and enhancing the existing automation systems, designing and developing new automation systems, software integration, and product validation. The candidate will also work closely with cross-functional teams to diagnose and resolve problems. Qualifications: BE/BTech/ME/MS/MTech in CS / IT / E&C Experience and Technical Skills required Exp: 5+yrs Using Linux OS. Linux admin experience is a plus. Strong coding capability in scripting languages, Python, Perl or bash etc. Build systems based on Makefiles and gcc Version control tools such as git/Perforce/CVS etc. Experience with Jenkins or other CI tools Familiarity with job scheduler software like Slurm, LSF, or PBS. Experience with Parasoft or other static code analyzers Ability to clearly communicate and document technical problems and solutions Ability to multi-task and prioritize work Experience with containers and K8 is a plus Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity
As a Verification IP (VIP) Developer at our company, you will be responsible for the design, development, verification, and deployment of Verification IP (VIP). You should have 2 to 5 years of domain experience and possess proficiency in functional verification. Your role will involve creating test environments using SV/UVM with strong debug skills. Additionally, hands-on knowledge of C/C++/Scripting is required, along with working experience on layered Protocols such as UCIe, PCIe, CXL, Ethernet. Prior experience with VIP usage and development would be a plus. Strong Digital Electronics and Programming fundamentals are essential for this position. We are looking for self-motivated individuals with strong analytical and communication skills. Qualifications: - BE/BTech/ME/MS/MTech in Electrical/Electronics,
You will be a Sr Principal Physical Design Engineer based in Bengaluru, responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on the latest Tech nodes. Your day-to-day tasks will include floorplanning, placement, clock tree synthesis, routing, and physical verification. Additionally, you will collaborate with cross-functional teams, mentor junior engineers, and ensure the design meets performance, power, and area specifications. Key Responsibilities: - Strong expertise in floorplanning, placement, clock tree synthesis, routing, and physical verification - Utilize physical design tools like Cadence Innovus, Synopsys ICC2, or similar - Proficiency in scripting languages such as TCL, Perl, and Python for design automation - Knowledge of timing analysis, signal integrity, and power analysis - Demonstrate excellent problem-solving skills and attention to detail - Strong communication and collaborative skills Qualifications: - Bachelors or Masters degree in Electrical Engineering or related field - 11-15 years of relevant experience in physical design - Experience in leading and mentoring a team (Note: No additional details of the company were present in the provided job description.),