Lead STA & Synthesis Design Engineer

As a Physical Design Engineer with 5-12 years of experience, your role involves working on challenging DDR PHY IP & Testchip Physical Design below 7nm technology nodes. You will take ownership of physical design blocks including floorplan, CTS, PNR, QRC, STA, PV & IR. Additionally, you will contribute to design methodology, flow automation, and innovate & implement Power, Performance, and Area optimization techniques. Your participation in IP release to customers and support team on standardizing & documenting learnings will be crucial. **Key Responsibilities:** - Work on challenging DDR PHY IP & Testchip Physical Design below 7nm technology nodes - Take ownership of physical design blocks including floorplan, CTS, PNR, QRC, STA, PV & IR - Contribute to design methodology and flow automation - Innovate & implement Power, Performance, and Area optimization techniques - Participate in IP release to customers and support team on standardizing & documenting learnings **Qualifications Required:** - Bachelors degree in Electronics or equivalent practical experience - 3+ years of experience and in-depth knowledge of Netlist-GDS physical design - Experience on sub 7nm tech nodes - Good hands-on experience with scripting in tcl & python In addition, preferred qualifications include experience in hardening DDR PHY designs, physical synthesis, and constraints design. Experience in Cadence tools such as Innovus, Genus, Tempus & Voltus, as well as RDL routing, PERC ESD checks, and knowledge of lower Tech node N3, Samsung N5, N4 would be a plus. This job offers you the opportunity to work on cutting-edge technology nodes, contribute to challenging projects, and continuously enhance your skills in physical design and optimization techniques.,