101 Floorplanning Jobs - Page 4

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understandin...

As an IO Layout specialist, you will be responsible for designing and verifying GPIO library layouts. Your expertise in floorplanning, placement, IO ring implementation, and IO bus design will be crucial in ensuring the efficient functioning of the layout. With at least 3 years of experience in the field, you will bring valuable insights and knowledge to the team. To excel in this role, you should hold a BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or a related field. Your educational background will provide you with the necessary foundation to tackle the challenges associated with IO layout design. Join us in Bangalore, Hyderabad, or Noida, and be a p...

THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps...

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field. We are seeking PDN engineers with EMIR and PG planning expertise and a mi...

Qualcomm India Private Limited is seeking a CPU Integration CAD Engineer to join the Engineering Group, specifically in the Hardware Engineering department. As part of the NUVIA team, which is now integrated into Qualcomm, you will be involved in reimagining silicon and developing computing platforms that aim to revolutionize the industry. This role offers the opportunity to collaborate with exceptionally skilled engineers to design innovative solutions that excel in performance, energy efficiency, and scalability. To qualify for this position, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 6 yea...

THE ROLE: The focus of this role in the AECG ASIC organization is to own physical design implementation for next generation ASICsthat meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. I...

THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICsthat meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role th...

THE ROLE: As a PD Manager, you will drive Physical design implementation and execution for next generation SOCs. You will manage PD team for end-to-end PD execution. You will work closely with the SOC architects, Physical design architects/leads, Design leads, IP teams to achieve first-pass silicon success. You will be expected to lead design implementation and convergence activities in the backend from a PnR implementation perspective. The SOCs are based off the most complex process technologies It's a great opportunity to join the talented team that is well-invested in the implementation of futuristic designs in advanced process nodes. THE PERSON: You will be responsible for driving a team...

KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 7+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power...

Qualcomm India Private Limited is seeking a Hardware Engineer to join their Engineering Group, specifically focusing on Hardware Engineering. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams to meet performance requirements is a key aspect of this role. Key responsibilities for this position include: - IR Signoff CPU/high performance cores - Signal EM & Powe...

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Col...

You should have at least 3+ years of relevant experience leading SoC Physical design projects across multiple technology nodes, including 5nm for TSMC and other foundries. Your expertise should include hands-on Place and Route (P&R) skills with in-depth knowledge of ICC/Innovus. You must possess expert knowledge in all phases of Physical Design (PD) from Synthesis to GDSII, with a solid background in Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and strong familiarity with the top level at the latest technology nodes will be beneficial. Collaboration with CAD, Met...

The Sr. Staff Physical Design Engineer position at Lattice Semiconductor in Pune, India offers a dynamic opportunity to join the HW design team focused on IP design and full chip integration. As part of a worldwide community of engineers and specialists, you will have the chance to contribute, learn, innovate, and grow within this fast-paced and ambitious organization. Key responsibilities for this role include implementing and leading the RTL to GDSII flow for complex designs, working on various aspects of physical design such as place & route, CTS, routing, floorplanning, powerplanning, timing, and physical signoff. The ideal candidate will have experience in physical design signoff checks...

You should possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, including tasks such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. It is essential to have experience with Physical Design Methodologies and sub-micron technology, particularly in 16nm and lower technology nodes. Moreover, you should have expertise in Analog and Mixed Signal Design and be familiar with handling designs with more than 5M instance count and operating at a frequency of 1.5GHz. Proficiency in programming languages such as Tcl, Tk, and Perl is require...

As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with a minimum of 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of exper...

You should have at least 3+ years of relevant experience in SoC Physical design, with a focus on multiple technology nodes including 5nm for TSMC and other foundries. Your expertise should include hands-on P&R skills, particularly in ICC/Innovus. You must possess expert knowledge in all aspects of Physical Design (PD) from Synthesis to GDSII, with a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and working at the top level in the latest technology nodes will be highly beneficial. Collaboration with CAD, Methodology & IP teams for PD implementation is critical, requi...

Quest Global is a leading organization known for its innovation and rapid growth in the engineering services sector. With a rich domain expertise and a strong presence in the top OEMs across seven industries, we are a company with a 25-year legacy and a vision to reach a centennial milestone. Driven by ambition, passion, and humility, we are on a journey to shape the future through engineering. We are in search of individuals who embody the spirit of humble geniuses, believing in the power of engineering to turn the impossible into reality. Our ideal candidates are innovators inspired by technology and driven to design, develop, and test solutions as trusted partners for Fortune 500 clients....

Position Summary Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis, Place and Route, STA, timing and physical signoffs Role and Responsibilities Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block le...

Lead and execute Analog Mixed-Signal layout design for high-speed DDR/HBM IPs Deliver robust and high-quality physical layout designs ensuring adherence to DDR/HBM specs Apply deep understanding of FinFET and CMOS technology at 28nm and below Handle high-speed digital layout verification with attention to signal integrity Implement advanced floorplanning techniques and apply submicron mitigation strategies Coordinate with remote layout teams globally for layout quality and deliverables Drive internal flow adherence for tape-out readiness and schedule compliance Collaborate with PHY designers, package engineers, and system teams to meet design objectives Oversee IO layout requirements includi...

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Creating floorplans, routing, and performing physical verifications to meet quality standards. Debugging and solving complex layout issues to ensure high-quality deliverables. Collaborating with design engineers to optimize layout for performance, power, and area. Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. Ensuring compliance with DRC, LVS, ERC, and antenna rules. The Impact You Will Have: Contribute to the development of cutting-edge technologies that drive the Era of Smart Everything. Enhance the performance and reliability of next-generation semiconductor IPs. Accelerate the ti...

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floorplanning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-ma...

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floor planning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-m...

Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelor s degree with at least 1-3 years of design/EDA experience or Master s degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred....

Description We are seeking a highly skilled ASIC Physical Design, Sr Staff Engineer to join our team in India. In this role, you will be responsible for the physical design and implementation of high-performance ASICs, collaborating closely with cross-functional teams to ensure successful project delivery. Responsibilities Design and implement physical layouts for ASIC designs. Conduct place and route activities to meet timing and area requirements. Perform timing analysis and optimization to ensure high-performance ASICs. Collaborate with RTL designers to ensure design feasibility and manufacturability. Utilize EDA tools for physical design tasks such as Cadence, Synopsys, or Mentor Graphic...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Mast...