Senior Physical Design Lead /Manager

As a Physical Design Lead, you will be responsible for overseeing the RTL-to-GDSII flow for advanced technology nodes (7nm and below). Your role will include leading the physical implementation of SoC/IP, driving PPA goals, and ensuring successful tapeouts. You will be managing a team, collaborating with cross-functional groups, and taking ownership of block/top-level execution. Key Responsibilities: - Perform floorplanning, placement, clock tree synthesis (CTS), routing, and signoff - Conduct static timing analysis (STA), handle IR/EM, power & physical verification - Utilize EDA tools such as Innovus, PrimeTime, Calibre, etc. - Proficiency in scripting languages like TCL/Perl/Python, UPF, and handling ECOs - Demonstrate strong leadership skills and effective communication within the team Qualifications Required: - Proven experience in RTL-to-GDSII flow for advanced technology nodes - Familiarity with tools like Innovus, PrimeTime, Calibre, etc. - Proficiency in scripting languages such as TCL/Perl/Python and experience with UPF and ECOs - Strong leadership and communication skills to effectively manage a team and collaborate with cross-functional groups (Note: No additional details about the company were provided in the job description.),