Like Requirements: 5 to 10 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG, MBIST Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

Job Description Hand-on experience and Comprehensive knowledge of Static Timing Analysis. Hands-on experience in Logical aware Synthesis, Logical Equivalence check and, Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge in the Timing closure on Sub-system level & Block level and Chip level. Knowledge in writing Manual ECOs to fix timing violations and DRCs. Knowledge of constraint development. Good Knowledge of TCL scripting and UNIX env. Leading the team of 4 to 5 team members by guiding and mentoring on the STA /Synthesis. Pre-layout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs final tape-out timing closure skills across corners and modes Must work with RTL design team, PD team, and HMs team for overall timing closure for SoC

Analog Mixed Signal Circuit Designer Role - Lead / Principal Engineer / Director Desired Experience and Skills In-depth understanding and practical experience in analog mixed-signal circuit design, including areas such as PLL, DLL, CDR, transceivers, clocking circuits, data converters, LDO, BG, DC-DC converters, and high-speed circuits (USB, DDR, SerDes). Proven hands-on experience in transistor-level design and verification of analog circuits to meet functional and performance specifications. Skilled in leading technical teams, providing mentorship, and guiding engineers in execution and delivery. Knowledgeable in advanced process nodes and experienced in addressing design challenges during migration to newer technology/process nodes. Familiarity with modeling and AMS verification is a plus. Strong ability to communicate effectively and interact with customers. A collaborative team player.

Job Title: SoC Design lead/manager Expectation: 12+ Years of relevant industry experience in multiple SoC designs Strong technical background in driving SoC design independently Experience in processor system integration, NoC design and integration, Good understanding of high-speed protocols such as PCIe/DDR/HBM/Ethernet etc.. Strong experience with AXI/AHB bus protocols. Defining sign-off quality design constraints for SoC. Hands-on expertise with low-power design techniques such as UPF/CPF. Experience in Security aspects in SoC [secure JTAG, encryption/decryption] &secure boot design. Experience in Lint/CDC checks Hand-on experience in Verilog HDL, System Verilog, C/C++ Drive one or more teams for their respective deliverables. Ensure the quality of deliverables and take necessary steps to improve the quality Excellent analytical and problem-solving skills. Excellent communication skills to interact with cross-functional teams to build consensus. Good teamwork spirit and collaboration skills with team members. Education BTech or MTech or equivalent experience in Electronics Engineering.

Design Verification Engineer - Specialised in Protocol like; PCIe/Ethernet/DDR/LPDDR/HBM Location: Noida, UP / Bangalore, India Experience: 3-10 Years Job Description: Experience in interconnect protocol PCIe/ Ethernet. Experience in Memory protocol DDR/LPDDR/HBM; HBM is preferred. AXI/ACE/CHI understanding, [AXI is must] Understanding of DMA usage. Strong in SV/UVM. Experience in the usage of standard VIP in TBs (preferably Synopsys) AI/ML network understanding (good to have). Additional knowledge of perl/tcl scripting will be an advantage. Must Bachelors Degree in Electrical, Electronics or Computer Engineering

Job Overview: We are looking for a highly motivated and detail-oriented Block-Level Physical Design Engineer (4+ Years) to join our dynamic VLSI team. You will be responsible for driving the complete physical implementation of complex digital blocks using industry-standard tools and methodologies, targeting advanced technology nodes including 2 nm/3nm and beyond. Key Responsibilities: Execute block-level physical design activities including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing , and Physical Verification . Perform Static Timing Analysis (STA) , IR drop analysis, RC extraction , and ensure power, timing, and signal integrity closure. Work hands-on with tools like Cadence Innovus , Synopsys ICC2 , Primetime , RedHawk , etc. Handle congestion analysis , design optimization , and area/power/timing trade-offs to meet PPA targets. Collaborate with RTL design, DFT, and verification teams to ensure seamless integration and clean handoff. Contribute to timing closure , ECO implementation, and physical sign-off.