Like Requirements: 5 to 10 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG, MBIST Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.
Job Description Hand-on experience and Comprehensive knowledge of Static Timing Analysis. Hands-on experience in Logical aware Synthesis, Logical Equivalence check and, Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge in the Timing closure on Sub-system level & Block level and Chip level. Knowledge in writing Manual ECOs to fix timing violations and DRCs. Knowledge of constraint development. Good Knowledge of TCL scripting and UNIX env. Leading the team of 4 to 5 team members by guiding and mentoring on the STA /Synthesis. Pre-layout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs final tape-out timing closure skills across corners and modes Must work with RTL design team, PD team, and HMs team for overall timing closure for SoC
Analog Mixed Signal Circuit Designer Role - Lead / Principal Engineer / Director Desired Experience and Skills In-depth understanding and practical experience in analog mixed-signal circuit design, including areas such as PLL, DLL, CDR, transceivers, clocking circuits, data converters, LDO, BG, DC-DC converters, and high-speed circuits (USB, DDR, SerDes). Proven hands-on experience in transistor-level design and verification of analog circuits to meet functional and performance specifications. Skilled in leading technical teams, providing mentorship, and guiding engineers in execution and delivery. Knowledgeable in advanced process nodes and experienced in addressing design challenges during migration to newer technology/process nodes. Familiarity with modeling and AMS verification is a plus. Strong ability to communicate effectively and interact with customers. A collaborative team player.
Design Verification Engineer - Specialised in Protocol like; PCIe/Ethernet/DDR/LPDDR/HBM Location: Noida, UP / Bangalore, India Experience: 3-10 Years Job Description: Experience in interconnect protocol PCIe/ Ethernet. Experience in Memory protocol DDR/LPDDR/HBM; HBM is preferred. AXI/ACE/CHI understanding, [AXI is must] Understanding of DMA usage. Strong in SV/UVM. Experience in the usage of standard VIP in TBs (preferably Synopsys) AI/ML network understanding (good to have). Additional knowledge of perl/tcl scripting will be an advantage. Must Bachelors Degree in Electrical, Electronics or Computer Engineering
Job Title: SoC Design lead/manager Expectation: 12+ Years of relevant industry experience in multiple SoC designs Strong technical background in driving SoC design independently Experience in processor system integration, NoC design and integration, Good understanding of high-speed protocols such as PCIe/DDR/HBM/Ethernet etc.. Strong experience with AXI/AHB bus protocols. Defining sign-off quality design constraints for SoC. Hands-on expertise with low-power design techniques such as UPF/CPF. Experience in Security aspects in SoC [secure JTAG, encryption/decryption] &secure boot design. Experience in Lint/CDC checks Hand-on experience in Verilog HDL, System Verilog, C/C++ Drive one or more teams for their respective deliverables. Ensure the quality of deliverables and take necessary steps to improve the quality Excellent analytical and problem-solving skills. Excellent communication skills to interact with cross-functional teams to build consensus. Good teamwork spirit and collaboration skills with team members. Education BTech or MTech or equivalent experience in Electronics Engineering.
Job Overview: We are looking for a highly motivated and detail-oriented Block-Level Physical Design Engineer (4+ Years) to join our dynamic VLSI team. You will be responsible for driving the complete physical implementation of complex digital blocks using industry-standard tools and methodologies, targeting advanced technology nodes including 2 nm/3nm and beyond. Key Responsibilities: Execute block-level physical design activities including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing , and Physical Verification . Perform Static Timing Analysis (STA) , IR drop analysis, RC extraction , and ensure power, timing, and signal integrity closure. Work hands-on with tools like Cadence Innovus , Synopsys ICC2 , Primetime , RedHawk , etc. Handle congestion analysis , design optimization , and area/power/timing trade-offs to meet PPA targets. Collaborate with RTL design, DFT, and verification teams to ensure seamless integration and clean handoff. Contribute to timing closure , ECO implementation, and physical sign-off.
ofAbout the Job 3 to 8 years of relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and preferably hands on experience on SoC STA, Power, Physical Verification and other sign-off. Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills. Bachelor's Degree in Electrical, Electronics or Computer Engineering
Job Description Hand-on experience and Comprehensive knowledge of Static Timing Analysis. Hands-on experience in Logical aware Synthesis, Logical Equivalence check and, Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge in the Timing closure on Sub-system level & Block level and Chip level. Knowledge in writing Manual ECOs to fix timing violations and DRCs. Knowledge of constraint development. Good Knowledge of TCL scripting and UNIX env. Leading the team of 4 to 5 team members by guiding and mentoring on the STA /Synthesis. Pre-layout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs final tape-out timing closure skills across corners and modes Must work with RTL design team, PD team, and HMs team for overall timing closure for SoC
Overview: We are looking for a highly motivated and detail-oriented Block-Level Physical Design Engineer to join our dynamic VLSI team. You will be responsible for driving the complete physical implementation of complex digital blocks using industry-standard tools and methodologies, targeting advanced technology nodes including 7nm/5nm and beyond. Key Responsibilities: Execute block-level physical design activities including Floor planning, Placement, Clock Tree Synthesis (CTS), Routing , and Physical Verification . Perform Static Timing Analysis (STA) , IR drop analysis, RC extraction , and ensure power, timing, and signal integrity closure. Work hands-on with tools like Cadence Innovus , Synopsys ICC2 , Primetime , RedHawk , etc. Handle congestion analysis , design optimization , and area/power/timing trade-offs to meet PPA targets. Collaborate with RTL design, DFT, and verification teams to ensure seamless integration and clean handoff. Contribute to timing closure , ECO implementation, and physical sign-off. Required Skills & Qualifications: Bachelor's/Masters degree in Electronics/Electrical Engineering or related field. 3+ years of hands-on experience in block-level physical design . Strong understanding of ASIC physical design flow and concepts. Solid experience in timing analysis, power optimization , and layout closure . Proficiency in EDA tools such as Innovus, ICC2, Primetime, Redhawk, Calibre . Good scripting skills in TCL, Perl, Python for automation. Preferred Qualities: Experience with 7nm/5nm nodes (TSMC or equivalent). Familiarity with industry-standard PPA targets and sign-off processes. Excellent analytical, communication, and problem-solving skills. Join us to shape the next generation of semiconductor innovation
Role: Physical Design Engineer As a Physical Design Engineer , you will be responsible for executing block-level and full-chip Physical Design (PD) activities, ensuring PPA (Power, Performance, Area) targets and timing closure across multiple technology nodes. Key Responsibilities: Execute Floorplanning, Placement, CTS, Routing, and Timing Closure for block and chip-level designs. Perform Synthesis, DFT insertion, and ECO implementation as required. Work closely with front-end, STA, and DFT teams to achieve signoff-quality results. Conduct Power and IR drop analysis, DRC/LVS checks, and ensure clean tapeout. Handle multiple technology nodes (e.g., 5nm, 7nm, 12nm, 16nm, 28nm) and tool flows. Drive LEC checks , timing ECOs , and convergence of design closure metrics. Required Skills & Experience: 3+ years of experience in Physical Design (Block or Full Chip). Hands-on expertise with ICC2 / Innovus / Fusion Compiler / PrimeTime / Voltus / Redhawk tools. Strong understanding of timing, power, and congestion analysis. Experience in Advanced Nodes (16nm) preferred. Solid knowledge of Static Timing Analysis (STA) and Synthesis flow. Excellent debugging and analytical skills.
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