Physical Design Engineer

Overview:

Key Responsibilities:

• Execute block-level physical design activities including

  Floor planning, Placement, Clock Tree Synthesis (CTS), Routing

  , and

  Physical Verification

  .
• Perform

  Static Timing Analysis (STA)

  , IR drop analysis,

  RC extraction

  , and ensure power, timing, and signal integrity closure.
• Work hands-on with tools like

  Cadence Innovus

  ,

  Synopsys ICC2

  ,

  Primetime

  ,

  RedHawk

  , etc.
• Handle

  congestion analysis

  ,

  design optimization

  , and

  area/power/timing trade-offs

  to meet PPA targets.
• Collaborate with RTL design, DFT, and verification teams to ensure seamless integration and clean handoff.
  
• Contribute to

  timing closure

  , ECO implementation, and physical sign-off.

Required Skills & Qualifications:

• Bachelor's/Masters degree in Electronics/Electrical Engineering or related field.
  

• 3+ years

  of hands-on experience in

  block-level physical design

  .
• Strong understanding of ASIC physical design flow and concepts.
  
• Solid experience in

  timing analysis, power optimization

  , and

  layout closure

  .
• Proficiency in EDA tools such as

  Innovus, ICC2, Primetime, Redhawk, Calibre

  .
• Good scripting skills in

  TCL, Perl, Python

  for automation.

Preferred Qualities:

• Experience with

  7nm/5nm

  nodes (TSMC or equivalent).
• Familiarity with industry-standard PPA targets and sign-off processes.
  
• Excellent analytical, communication, and problem-solving skills.
  

Join us to shape the next generation of semiconductor innovation