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Static Timing Analysis

Static Timing Analysis

7rays Semiconductors

4 - 9 years

1 - 6 Lacs

Bengaluru Greater Noida

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Skills Required

STA Static Timing Analysis Primetime ASIC Synthesis Synthesis Timing Analysis VLSI Timing Closure Lint Timing Lec

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Full Time

Job Description

Job Description Hand-on experience and Comprehensive knowledge of Static Timing Analysis. Hands-on experience in Logical aware Synthesis, Logical Equivalence check and, Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge in the Timing closure on Sub-system level & Block level and Chip level. Knowledge in writing Manual ECOs to fix timing violations and DRCs. Knowledge of constraint development. Good Knowledge of TCL scripting and UNIX env. Leading the team of 4 to 5 team members by guiding and mentoring on the STA /Synthesis. Pre-layout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs final tape-out timing closure skills across corners and modes Must work with RTL design team, PD team, and HMs team for overall timing closure for SoC

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7rays Semiconductors

www.7rays-semiconductors.com

Semiconductors

Silicon Valley

250 Employees

2 Jobs

Key People

John Doe

CEO
Jane Smith

CTO
Bill Lee

CFO

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