64 Asic Synthesis Jobs

Responsibilities: Block level or Top Level implementation experts from Netlist to GDSII. * Optimize physical design using STA, PNR, ICC, Primetime & TCL. * Manage floor planning, timing closure & LVS compliance. Provident fund Health insurance Food allowance Annual bonus

Design, develop, and improve software using various engineering methodologies. Ensure code is scalable, maintainable, and optimized for performance. Collaborate with product managers, designers, and other engineers to define software requirements. Participate in code reviews and promote a culture of code quality and knowledge sharing. Stay informed of industry technology trends and contribute to the organization's technology communities. Adhere to secure coding practices to mitigate vulnerabilities and protect sensitive data. Job Requirements Mandatory skills include Go Lang expertise, AWS Connect and lambda, and strong work experience in Dynamo DB. Java is an essential skillset for this rol...

RTL Design Location: Bangalore Experience- 4+ years Must have Hands-on experience and expert-level knowledge in RTL design and coding in Verilog and VHDL Hands-on experience and expert-level knowledge in SoC integration of ARM core-based designs Experience in working with AMBA Bus- AXI, AHB, APB. Experience in IP development: Standard Ips like PCIe Gen5 or Gen6, USB4.x, Ethernet, UCIe, HBM Hands-on experience and expert-level knowledge in ASIC Synthesis Hands-on Experience with Lint and CDC. Experience in equivalency checking Experience with FPGA based designs or FPGA prototyping In-depth understanding of Verilog/VHDL and ARM SoC architecture Hands-on experience and expert-level knowledge in...

As a Synthesis & STA Engineer, your role will involve performing RTL Synthesis to optimize the Performance/Power/Area of designs, implementing DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and conducting Validation. You will be responsible for creating Power Intent for designs, verifying power intent on RTL, running static Low-Power checks on gate level netlists, ensuring Logic Equivalency Checks between RTL to Gates and Gates to Gates, configuring signoff Static Timing Analysis and ECO flows, and achieving timing closure in collaboration with the Design/DFT/PD teams. Additionally, you will be involved in Power Analysis, estimating power ...

Hope you are doing well. We are currently hiring for an STA Engineer position at Eximietas Design , and based on your background, you may be an excellent fit for this role. Please find the detailed Job Description below. Job Description STA Engineer (Static Timing Analysis) Company: Eximietas Design Location: Bangalore Experience: 6+ Years About the Role: We are seeking an exceptional STA Engineer to join our semiconductor design team. You will collaborate with talented engineers to deliver high-performance, energy-efficient, and scalable ASIC designs. This role involves leading STA efforts for complex, high-speed, advanced-node ASICs in a fast-paced environment. Responsibilities: Lead a tea...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Overview: You will be responsible for securing an optimal digital IP and circuit by understanding required functions to be developed and designing and verifying them in line with the required goals. Your role will involve contributing in either SoC Clock/reset, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU, Host Subsystem, or Flash Subsystem based on your prior skills and desire to learn. Key Responsibilities: - Have 10 to 15 years of work experience in VLSI SoC RTL design. - Understand digital design principles, specifically AMBA SoC BUS protocols such as APB, AXI, and AHB. - Create micro-architecture and detailed design documents for SoC design considering performance, power, ...

Please find JD for required job profile. Bachelors or Masters Degree with a strong VLSI Background Minimum 4 years of experience in Synthesis . Worked on 7nm/5nm/Future sub-micron Technologies. Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus . Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or Formality. Familiar with pre-STA timing analysis using Primetime or Tempus. Familiar with low power check using Conformal Low Power or VCLP tool. Experience in verifying constraints quality and completeness. Understanding of UPF & Low power concepts...

- Design and implement physical layout of integrated circuits - Work closely with design team to ensure layout meets specifications - Perform physical design verification and optimization - Collaborate with cross-functional teams to ensure successful project completion - Stay up-to-date on industry trends and advancements in physical design technology Qualifications: - Bachelors degree in Electrical Engineering or related field - Proven experience in physical design of integrated circuits - Proficiency in CAD tools such as Cadence or Synopsys - Strong problem-solving skills and attention to detail - Excellent communication and teamwork abilities

Timing analysis, validation and debug across multiple PVT conditions using Tempus. Familiar with Tempus DMMMC flow for STA and logical/physical aware ECO flows focusing timing and leakage optimization. Peripheral timing checks. STA setup, convergence, reviews and signoff for multi-mode (func/scan/atspeed/atspeed exceptions), multi-voltage domain designs. Review of Unconstrained endpoints and check timing reports. Proficient in STA and timing methodologies with good understanding of noise, crosstalk, and OCV effects. Should have worked on both block level and full chip timing closure in 16nm, 5nm and below. Additionally, closely interact with designers/synthesis/PNR team to provide the feedba...

Proficiency in RTL designs using Verilog/SystemVerilog/VHDL based on specifications. Solid understanding of digital design concepts, including pipelining, clock domain crossing (CDC), and reset strategies. Experience with industry-standard tools for synthesis, linting, and STA (e.g., Synopsys Design Compiler, Mentor Questa, or Cadence Genus). Collaborate with system architects to understand requirements and translate them into micro-architectures. Perform design optimization for performance, power, and area (PPA). Work with verification teams to define test plans and debug issues in simulations and emulation environments. Address synthesis, timing, and functional issues through RTL modificat...

Title- RTL Technical Lead- VLSI Design Experience: 7-12 years Industry: Semiconductors / Electronics / VLSI Employment Type: Full Time We are seeking a highly skilled and motivated RTL Lead to join our VLSI design team. The ideal candidate will have strong expertise in SoC integration , RTL coding , and front-end design flows . You will be responsible for leading RTL development, driving integration efforts, and ensuring design quality across multiple projects. Roles and Responsibilities Lead RTL design and integration of complex SoC architectures using Verilog/SystemVerilog. Own and execute SoC integration tasks including IP stitching, bus protocols, and top-level connectivity. Perform stat...

Responsibilities: * Perform timing analysis using Primetime, Design Compiler & Genus. * Collaborate with design team on ASIC synthesis and timing closure. * Implement innovative techniques for improved performance. Health insurance Provident fund Food allowance

We are looking for a highly motivated and skilled Graduate Electrical Engineer with 2 to 4 years of experience to join our team at BuroHappold Engineering. The ideal candidate will have a strong foundation in electrical engineering principles and practices. Roles and Responsibility Design, develop, and test electrical systems, including power generation, transmission, and distribution. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop and implement electrical safety protocols and procedures to ensure compliance with industry standards. Conduct site visits to inspect and troubleshoot electrical systems and equipment. Provide technical support and...

We are looking for a skilled Full Stack Software Developer with 8 to 10 years of experience to join our team in Calypso Technology India Pvt. Ltd. The ideal candidate will have expertise in Java and React. Roles and Responsibility Design, develop, and test software applications using Java and React. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop high-quality, scalable, and efficient code. Troubleshoot and resolve technical issues efficiently. Participate in code reviews and contribute to improving overall code quality. Stay updated with industry trends and emerging technologies. Job Requirements Strong proficiency in Java and React. Excellent...

We are looking for a highly skilled and experienced Senior Research Associate to join our team at SRF Limited. The ideal candidate will have 4 to 8 years of experience in research and development, with a strong background in this field. Roles and Responsibility Conduct experiments and collect data to support research projects. Analyze and interpret complex data sets to draw meaningful conclusions. Develop and implement new research methods and techniques. Collaborate with cross-functional teams to achieve project goals. Prepare and present research reports and findings to stakeholders. Stay updated with industry trends and developments. Job Requirements Strong understanding of research princ...

RTL Design Engineer Job Location: Bengaluru (BLR) and Hyderabad (HYD) Experience: 7 to 20 years About The Role : We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of ARM Micro Architecture to join our team. In this role, you will play a key role in the development of complex digital designs and contribute to the success of our cutting-edge projects. The ideal candidate will have a proven track record in RTL design and a deep understanding of ARM Micro Architecture. Key Responsibilities: Collaborate with cross-functional teams to define and develop RTL designs for advanced microprocessor-based projects. Design, implement, and verify digital logic bloc...

Job Description Hand-on experience and Comprehensive knowledge of Static Timing Analysis. Hands-on experience in Logical aware Synthesis, Logical Equivalence check and, Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge in the Timing closure on Sub-system level & Block level and Chip level. Knowledge in writing Manual ECOs to fix timing violations and DRCs. Knowledge of constraint development. Good Knowledge of TCL scripting and UNIX env. Leading the team of 4 to 5 team members by guiding and mentoring on the STA /Synthesis. Pre-layout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closu...

As a Design Engineer, you will design synthesizable IP at the point of technology, for the latest PCIe, CXL standards. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Follow latest developments in PCIe standards Micro-architecture and design of advanced PCIe and CXL IP, for PCIe7 and beyond Participate in FPGA prototyping and hardware validation Run and improve quality checks (ASIC synthesis, CDC/RDC/Linting, simulation) Collaborate with a worldwide team Contribute to technical impr...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

What You''ll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for ...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

As an experienced professional with 2-6 years of expertise in micro architecture design and system design using Verilog, SV, or VHDL, you will play a crucial role in this position. Your responsibilities will include: - Utilizing Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. - Demonstrating familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C. - Conducting synthesis, timing analysis using various industry standard tools, and proficiency in TCL and Python scripting. To excel in this role, you should ideally possess...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...