37 Asic Synthesis Jobs

Summary: We are looking for an experienced Senior/Principal ASIC RTL Design Engineer with 10+ years of hands-on RTL design expertise to join our team in Bangalore. The ideal candidate will own end-to-end RTL design for complex SoCs or large subsystems, from micro-architecture through tapeout and silicon bring-up. Job Description: Own RTL design of SoC-level or large subsystems from specification to silicon bring-up. Define and implement micro-architecture; write high-quality, synthesizable RTL in SystemVerilog/Verilog. Work closely with physical design teams for synthesis, timing closure, power, area optimization, DFT hooks, and ECOs. Drive block/subsystem integration and ensure seamless bring-up. Collaborate with verification teams to define test plans, assertions (SVA), and coverage goals. Support silicon validation, post-silicon debug, and drive closure of design bugs. Apply low-power design techniques (UPF/retention/isolation) and clock/reset design best practices. Work on standard bus protocols like AXI/ACE/AHB/APB for interconnects, memory subsystems, and I/O integration. Deliver production ASIC tapeouts, owning critical blocks such as interconnects, coherency, memory subsystem, high-speed I/O, security, or power-management islands. Enhance design productivity using Tcl/Python scripting in service of RTL development. Required Skills: 10+ years of ASIC RTL design Proven track record of multiple production ASIC tapeouts. Expertise in SystemVerilog/Verilog, micro-architecture, clock/reset design, UPF, and low-power techniques. Strong knowledge of AMBA bus protocols AXI/ACE/AHB/APB. Hands-on experience with silicon bring-up and post-silicon debug.

Job Description: We are looking for Physical Design Engineer with 4+ years of experience for block-level implementation. The role involves PnR, timing closure, and logic implementation, ensuring high-quality designs that meet PPA goals. Required Skills: Perform block-level floor planning, placement, CTS, routing, and optimization. Execute PnR flows and close timing, congestion, power, and SI issues. Collaborate with RTL, DFT, and verification teams for smooth integration. Run STA and ensure block-level timing closure. Support top-level integration and resolve ECOs. Ensure compliance with design rules (DRC/LVS). Drive PPA optimization across blocks. Proficiency in ICC2 / Innovus or equivalent tools. Knowledge of logic equivalence checks and ECO flows. Familiar with low-power design and scripting (TCL, Perl, Python)

Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Job Description Position: DFT Lead Location: Bangalore, India Duration: Full Time Responsibilities: Responsible for writing timing constraints, running synthesis and implementing DFT (including scan, MBIST and IP testing), you will work on the company s next generation 5G IC and interact with software, signal processing algorithms, integration and layout teams. Requirements: At least 8 years experience of ASIC synthesis (including writing SDC), DFT (including scan and MBIST) and equivalence check, ideally with Cadence tools. Knowledge of CPF and Cadence CLP is a bonus. Highly motivated, pro-active self-starter. Strong sense of ownership and responsibility. Creative thinker with strong problem solving skills. Team oriented attitude and ability to thrive in a multicultural environment. Excellent written and oral communications skills. Qualifications: Bachelor s degree or higher in Computer Science or a related field. 8+ years of experience.

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Job Description: Strong understanding of Physical Design with hands-on experience in RTL2GDS flow. Ability to close tiles/blocks including timing, noise, power, IR, phyV, conformal equivalence, and signoff checks. Exposure to advanced technology nodes (7nm and below) and related design challenges. Experience with the Synopsys tool suite is required. Knowledge of high-frequency design (>2GHz)

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 8+/6+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills.

We are looking for a skilled RTL Design Engineer with 3 to 7 years of experience to join our team at Capgemini Technology Services India Limited. The ideal candidate will have a strong background in IT Services & Consulting and be proficient in RTL design. Roles and Responsibility Design and develop high-quality RTL code for various projects. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop and maintain technical documentation for RTL designs. Troubleshoot and debug issues related to RTL code. Participate in code reviews and ensure adherence to coding standards. Stay updated with industry trends and emerging technologies in RTL design. Job Requirements Strong understanding of digital logic design principles and methodologies. Proficiency in programming languages such as Verilog or VHDL. Experience with RTL design tools and software. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment. Strong communication and interpersonal skills.

As a Senior Director of Digital Design for New Product Development in Power Management at OnSemi in Bengaluru, India, you will be responsible for working on the development of power management products such as DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches, and efuses for consumer, industrial, and automotive applications. Your role will involve collaborating with various product lines for RTL implementation of power converter controller design, digital design architecture, low power design, synthesis, timing analysis, and physical design interface for power management chips. You will work as part of a large team of engineers and collaborate with design architects, digital verification, project management, and digital/analog design teams globally. Your responsibilities will include implementing micro-architecture to RTL implementation, supporting the bring-up of features in pre-silicon platforms, owning the technical outcome of design, verification, and implementation of Power Management ICs, understanding project goals, leading and supporting customer issues, production issues, FW and system development, and supporting post-silicon validation activities. To qualify for this position, you should have a BS/MS in Electrical Engineering or a related field with 18/20 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate should have a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages. OnSemi, a company focused on automotive and industrial end-markets, is committed to driving disruptive innovations in megatrends such as vehicle electrification, safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a portfolio of intelligent power and sensing technologies, OnSemi aims to create a safer, cleaner, and smarter world. If you are a high-performance innovator looking to join a dynamic team in a forward-thinking company, OnSemi offers a positive recruitment experience and attractive company benefits. More details about the benefits can be found here: [OnSemi Career Benefits](https://www.onsemi.com/careers/career-benefits).,

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities Defining chip and macro level power domains System Level Power Modeling Mixed signal power analysis Power Island/Power Gating/Power Isolation Structural Low power design of level shifter and isolation cell topology and associated rules Architectural analysis and development of digital power optimization logic/circuits/SW Work with Power Management IC developers for power grid planning Creating detailed architecture and implementation documents Education Requirements RequiredBachelor's, Computer Engineering and/or Electrical Engineering PreferredMaster's, Computer Engineering and/or Electrical Engineering Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs. Skills/Experience At least 4-12 years of experience are required in the following areas Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist/PTPX,Calypto) Power dissipation and power savings techniques- Dynamic clock and voltage scaling Power analysis (Leakage and dynamic) and thermal impacts Power Software features for power optimization Voltage regulators including Buck and Low Drop out ASIC Power grids and PCB Power Distribution Networks Additional skills in the following areas are a plus: Mobile Baseband application processors chipset and power grid understanding UPF-based synthesis and implementation using Design Compiler Structural low power verification tools like CLP or MVRC Outstanding written and verbal communication skills Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Synthesis. Experience: 3-5 Years.

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

As an experienced VLSI SoC RTL designer with 10 to 15 years of work experience, you will play a crucial role in securing an optimal digital IP and circuit. Your responsibilities will include designing and verifying functions in alignment with the required goals. You will have the opportunity to contribute to various areas such as SoC Clock/reset, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU, Host Subsystem, and Flash Subsystem based on your skills and interests. To excel in this role, you should have a strong understanding of digital design principles, with specific knowledge of AMBA SoC BUS protocols like APB, AXI, and AHB. Your tasks will involve creating micro-architecture and detailed design documents for SoC design while considering performance, power, and area requirements. Proficiency in debugging and experience with DV tools such as Verdi and NCSIM will be essential. Preferred candidates will have SOC integration experience at the Top Level, Block Level, or Subsystem level. Collaboration with the DV team to enhance verification coverage and working on GLS closure with DV, PD, and Modelling team will be part of your responsibilities. Knowledge of clock domain crossing (CDC), Linting, UPF, ASIC Synthesis, static timing reports analysis, and formal checking is required. Furthermore, you will be involved in defining constraints and ensuring critical high-speed path timing closure in collaboration with back-end teams. If you are seeking a challenging opportunity to leverage your VLSI SoC RTL design skills and contribute to cutting-edge projects, this role offers a stimulating environment to grow and excel.,

Job Location: Bengaluru (BLR) and Hyderabad (HYD) Experience: 7 to 20 years : We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of ARM Micro Architecture to join our team. In this role, you will play a key role in the development of complex digital designs and contribute to the success of our cutting-edge projects. The ideal candidate will have a proven track record in RTL design and a deep understanding of ARM Micro Architecture. Key Responsibilities: Collaborate with cross-functional teams to define and develop RTL designs for advanced microprocessor-based projects. Design, implement, and verify digital logic blocks and modules in accordance with project specifications and quality standards. Utilize your expertise in ARM Micro Architecture to optimize and enhance design efficiency. Perform RTL simulations and conduct thorough functional and timing analysis. Identify and resolve design issues, ensuring the delivery of high-quality RTL designs. Stay up-to-date with industry trends and emerging technologies to continually improve design methodologies. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience as an RTL Design Engineer with 7 to 20 years of relevant work experience. Strong knowledge of ARM Micro Architecture and its application in RTL design. Proficiency in RTL design tools and methodologies. Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS). Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work effectively in a dynamic and fast-paced environment. If you are a highly motivated and experienced RTL Design Engineer with a passion for innovation and a strong background in ARM Micro Architecture, we encourage you to apply for this exciting opportunity. Join our team and contribute to the development of cutting-edge technology solutions. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Calling all innovators and creators!Were hiring RTL Design Engineers for Bangalore to work on complex ASICdesigns and integrations.Experience Required3"“25 YearsKey Skills: RTL design, low-power methodologies, scripting (Perl, Python, TCL)Join us and design the future of technology! Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

About Us: Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolves Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities. Tessolves clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com. Job Overview Job Description: We are seeking a highly skilled and experienced Lead STA (Static Timing Analysis) Engineer to join our team in Bangalore. The ideal candidate will have deep expertise in timing closure for high-speed designs and hands-on experience with Synopsys timing tools. Key Responsibilities: Lead STA efforts for complex SoC designs at advanced nodes (3nm and below) Perform timing analysis and closure using Synopsys PrimeTime and FusionCompiler Work on high-speed interfaces including 100G Ethernet and PCIe Gen6 Collaborate with design, physical implementation, and verification teams to resolve timing issues Develop and maintain timing constraints and methodologies Ensure timing sign-off quality and compliance with project requirements Required Skills & Experience: 8–12 years of experience in Static Timing Analysis Strong hands-on expertise with Synopsys STA tools (PrimeTime, FusionCompiler) Proven experience in high-speed SERDES designs (GHz+ frequencies) Familiarity with TSMC 3nm or similar advanced process nodes (preferably 5nm and below) Solid understanding of digital design, timing constraints, and physical design flow Excellent problem-solving and communication skills

The position requires 2-6 years of experience with micro architecture design and system design using Verilog, SV, or VHDL. You should also have experience in Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. Familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C is essential. You will be responsible for synthesis, timing analysis using various industry standard tools, and should have proficiency in TCL and Python scripting. The ideal candidate for this role should have a notice period of immediate availability to 1 month. The position is based in BLR/Hyd locations.,

Since June 2021, frog is part of Capgemini Invent . frog partners with customer-centric enterprises to drive sustainable growth, by building and orchestrating experiences at scale, while harnessing the power of data and technology. Were inventing the future of customer experiences by delivering market-defining business models, products, services, brand engagements and communications. Joining frog means youll be joining the pond, a global network of studios, each with a thriving in-person and vibrant virtual culture. frogs are curious, collaborative, and courageous, united by our passion for improving the human experience across our areas of expertise, while each bringing our unique and diverse skills and experiences to the table. We draw on our global reach and local knowledge to solve complex problems and create innovative, sustainable solutions that touch hearts and move markets. frogs prize humour, positivity, and community just as highly as performance and outcomes. Our culture is open, flexible, inclusive, and engaging. Working at frog means being empowered to meet the moment, and Make Your Mark on every project, in your studio, your community and the world at large. Equal Opportunities at frog Frog and Capgemini Invent are Equal Opportunity Employers encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We are seeking a highly skilled and experienced Sub-System Hardware Architect specializing in ASIC design for AI to join our dynamic team. The ideal candidate will have a strong background in hardware design and architecture, with a focus on AI sub-systems. This role involves defining and leading the hardware architecture for ASIC components within the Turing subsystem, ensuring they meet performance, reliability, power, and scalability requirements. Desired Skillset: Proven experience in designing and developing ASIC sub-system hardware components for AI applications. Strong knowledge of ASIC design tools and methodologies. Excellent problem-solving and analytical skills. Ability to work effectively in a team environment. Strong communication and interpersonal skills. Expertise in writing detailed hardware specifications and good documentation practices. Knowledge of micro-architecture, RTL coding, and clock controller design. Strong understanding of low power designs and strategies. Excellent written and verbal communication skills. Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 8 to 12 years of experience in ASIC design and architecture. Principal Duties and Responsibilities: Define sub-system hardware architecture, covering performance, power strategies, etc. Collaborate with cross-functional teams, including Product, Software, SOC, and Hardware Implementation teams, to define hardware requirements and specifications. Develop and implement ASIC hardware architecture strategies for AI. Conduct power assessment and set power targets as part of the architecture work. Conduct studies to improve performance and identify bottlenecks. Write detailed and precise hardware specifications and maintain thorough documentation. Conduct feasibility studies and risk assessments for ASIC designs. Perform detailed analysis and optimization of ASIC hardware performance. Provide technical guidance and mentorship to junior engineers. Stay updated with the latest advancements in ASIC technology and AI applications. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/SystemVerilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment.

Job Description : Hands on experience in Block level PnR convergence with Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus In this position, candidate is expected to lead all block/chip level PD activities including floor plans, placement, CTS, optimization and routing techniques, RC extraction, STA, EM/IR DROP, PV Familiar with deep sub-micron designs below 10nm preferred BE/B Tech/ME/M TECH

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less