13 Icc2 Jobs

Providing Customer Support and Collaborating with R&D teams to drive product development for wide deployment. Demonstrating differentiated PPA results to showcase our technologys superiority. Providing technical support to key global customers to address PPA bottlenecks and design challenges on the most advanced designs. Aggressively engaging in worldwide critical benchmarks and deployments to ensure the highest quality and performance of designs. Utilizing scripting languages such as Perl and Tcl for automation and optimization tasks. Staying updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve processes. The Impact You Will Have: Enhancing the performance and efficiency of Fusion Compiler designs. Driving innovations that contribute to the success of Synopsys cutting-edge technologies. Providing critical support that helps key customers overcome their PPA challenges. Contributing to the development of new features that keep Synopsys at the forefront of the industry. Improving the overall quality and reliability of our products through meticulous design and optimization. Fostering strong relationships with global customers, reinforcing Synopsys reputation as a leader in chip design and software security. What You ll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience. Hands-on experience with synthesis and place and route (P&R) tools. Proficiency with EDA tools such as DC, FM, ICC2, and Fusion Compiler. Knowledge of advanced placement and routing rules. Experience with scripting languages like Perl and Tcl. Strong understanding of ASIC design flow, VLSI, and CAD development. Never give-up attitude and flexibility in supporting worldwide engagements. Who You Are: Excellent communicator with strong command of English. Highly motivated and self-driven. Detail-oriented with a focus on quality and performance. A team player who thrives in collaborative environments. Adaptable and eager to learn new technologies and methodologies.

What Youll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience, Hands-on experience with synthesis and place and route (P&R) tools, Proficiency with EDA tools such as DC, ICC2, and Fusion Compiler, Knowledge of advanced placement and routing rules, Experience with scripting languages like Perl and Tcl, Strong understanding of ASIC design flow, VLSI, and CAD development, Never give-up attitude and flexibility in supporting worldwide engagements, Who You Are: Excellent communicator with strong command of English, Highly motivated and self-driven, Detail-oriented with a focus on quality and performance, A team player who thrives in collaborative environments, Adaptable and eager to learn new technologies and methodologies,

What Youll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience, Hands-on experience with synthesis and place and route (P&R) tools, Proficiency with EDA tools such as DC, ICC2, and Fusion Compiler, Knowledge of advanced placement and routing rules, Experience with scripting languages like Perl and Tcl, Strong understanding of ASIC design flow, VLSI, and CAD development, Never give-up attitude and flexibility in supporting worldwide engagements, Who You Are: Excellent communicator with strong command of English, Highly motivated and self-driven, Detail-oriented with a focus on quality and performance, A team player who thrives in collaborative environments, Adaptable and eager to learn new technologies and methodologies,

Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level) Active participation in post silicon validation, correlation and test activities using in-house test and validation lab Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow Perform custom RF Physical Design, including block-level and top level layouts, floorplanning, package routing Supports complex projects or leads smaller independent design activities Support CAD and drawing updates on both sustaining/new project with minimal supervision Contributes to PD architecture/Plug-In Unit at the unit level

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Staff Physical Design Engineer • Job Description o Be part of a diverse team working on the high performance designs. Youll lead the complex multimillion instance subsystems including high-speed blocks i.e. DDR, PCIe, AI Cores • Technical Requirements o 8-12 years of experience in Physical Design o Expert in PnR, sign off convergence including timing, physical and PDN verification o Experience in sub 5nm technology node with high performance designs o Experience in pushing performance by custom PnR techniques o Expert of STA and eco generation PnR steps o Expert in debugging and fixing flow, tool and design related issues independently o Experience in the solving physical integration design challenges o Expertise in industry standard tools like Innovus/ICC2/Fusion compiler/Primetime o Experience in contributing to physical design flows and methodologies o Expertise in automation scrips(TCL/PERL/Python)for various implementation steps o Experience in leading and mentoring a team o Ability to work cross-functionally with various teams • Academic Credentials o Qualification: Bachelors or Masters in Electronics/Electrical Engineering

Staff Power Delivery Network and Reliability Engineer Mulya Technologies Greater Bengaluru Area (Hybrid) Staff Power Delivery Network and Reliability Engineer Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Power Delivery Network and Reliability Engineer Expertise in Power Grid design and in-depth knowledge of IR drop & EM(electromigration) concepts Knowledge of PDN tool algorithms and hands-on experience with industry-standard tools like Voltus and Redhawk/Redhawk-SC, Exposure to implementation tools like Innovus/ICC2 is a plus Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Job description Location: Bangalore, Hyderabad Experience: 3 to 15 years Notice Period: Immediate to 30days Job Description: • Have good knowledge of entire physical design process from floorplan till GDS generation • Good Exposure to Physical Verification Process • Have hands-on experience in latest sub-micron technologies below 10 nm • Hands on experience in leading PnR tools Synopsys ICC/ICC2 • Experience in low power designs and handling congestion or timing critical tiles will be preferred • Experience in ECO implementation preferred • Scripting skills in Perl/Tcl/Python etc

Job description Location: Bangalore, Hyderabad Experience: 3 to 15 years Notice Period: Immediate to 30days Job Description: • Have good knowledge of entire physical design process from floorplan till GDS generation • Good Exposure to Physical Verification Process • Have hands-on experience in latest sub-micron technologies below 10 nm • Hands on experience in leading PnR tools Synopsys ICC/ICC2 • Experience in low power designs and handling congestion or timing critical tiles will be preferred • Experience in ECO implementation preferred • Scripting skills in Perl/Tcl/Python etc

BE / BTech / ME / MTech in ECE with 4+ years of relevant experience in ASIC PD. Expertise in digital physical design Expertise in EDA synthesis, APR, STA tools and methodologies Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk Hands on experience of working with multi modes and multi corners STA Working Knowledge of multiple power planes and multiple VT libraries Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification Good at scripting languages PERL, TCL, shell Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs Experience in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization Experience in making ECOs both Metal and logic level ecos Experience DRC and LVS cleanup of designs during sign off Exposure to lower node technologies 16nm or below preferred

Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level) Active participation in post silicon validation, correlation and test activities using in-house test and validation lab Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow Perform custom RF Physical Design, including block-level and top level layouts, floorplanning, package routing Supports complex projects or leads smaller independent design activities Support CAD and drawing updates on both sustaining/new project with minimal supervision Contributes to PD architecture/Plug-In Unit at the unit level

He/she should be able to help other junior engineers within the team. This role is for a technical ladder and so it requires hands-on working knowledge preferably with SNPS tools like DC, PT, PT-SI and ICC2. Typically requires 4-7 years of experience after graduation from a reputed university. Should be strong in technical concepts, fundamentals, and good team player. The role involves daily technical interaction with local, US counter parts. He/she will be part of SNPS DDR, HBM, UCIe IP implementation team and responsible for the implementation and integration of world class Die-to-Die IPs at the cutting-edge technology nodes (14nm,10nm,7nm,5nm and below). Timing closure above ~2GHz, mixed signal had macro-IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/UCIe timing closure, implementation would be an added advantage.