1850 System Verilog Jobs - Page 10

Role & responsibilities Be part of a team to verify complex system on a chip designs. Interact with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using UVM/ SystemVerilog Create complex C/SV tests using reusable test libs. Team player and a mentor who is self-driven, motivated and guides a team of junior engineers Responsible for quality and timeliness of the team output Preferred candidate profile Bachelor's/ master's degree in electrical engineering or computer science, with 5-10 years of relevant experience. Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity ...

This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage. Skills/Experience Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including: functional and structural RTL design, design partitioning, simulation and regression, collaboration wi...

General Summary: This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage. Skills/Experience Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including: functional and structural RTL design, design partitioning, simulation and regression,...

General Summary: Senior/Lead ASIC Verification Engineers with an experience of minimum 5+ yrs Very strong experience with Verilog, System Verilog and UVM Working experience on development of Verification IP of layered protocol High Speed peripheral Interface protocol PCIe Gen4+ onwards, PCIe Experience is a must Strong knowledge on UVM RAL and common register interfaces such as APB, AHB, AXI (ARM), RAM. Working experience on scripting and automation Strong Past experience of developing verification plan from scratch and testbench development using the detailed Specification and TestPlan from the scratch Strong base knowledge on digital design, blocks/components Strong debugging skills and Go...

General Summary: Work with Qualcomm's engineering team to develop Performance Models for the next generation System-on-chip (SoC) for smartphone, IoT, Auto and other product categories. Work with design team to develop IP Models for Peripherals like PCIe, Ethernet, USB, UFS. Develop the SoC platform and verify the IP/System Level use cases. Work with Hardware & Software teams to understand the design requirements, specification and interface details. You will have opportunity to suggest architecture and design changes which can optimize the overall power/performance/thermal for the chipset. The successful candidate will - Be part of Qualcomm performance team. Some of the key skills which are...

General Summary: Work with Qualcomm's engineering team to develop Performance Models for the next generation System-on-chip (SoC) for smartphone, IoT, Auto and other product categories. Work with design team to develop IP Models for Peripherals like PCIe, Ethernet, USB, UFS. Develop the SoC platform and verify the IP/System Level use cases. Work with Hardware & Software teams to understand the design requirements, specification and interface details. You will have opportunity to suggest architecture and design changes which can optimize the overall power/performance/thermal for the chipset. The successful candidate will - Be part of Qualcomm performance team. Some of the key skills which are...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity ...

We're Hiring Lead Verification Engineer Location: Ahmedabad(Preferable) /Bengaluru Are you passionate about building robust verification environments and working on cutting-edge SoC designs? Join our team and help shape the future of semiconductor innovation! Key Responsibilities • Develop verification plans and test infrastructure for SoC/IP subsystems • Create test benches and test cases using Verilog, System Verilog, UVM, C, and Formal methods • Write embedded C code and CPU-centric tests • Define, implement, and analyse functional coverage Qualifications • M.E./B.E. in Electronics Engineering with 8+ Years of Experience • Strong knowledge of UVM, C testbenches, assertion-based and formal...

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, Responsibilities: Develop and implement DFT architectures and strategies for complex SoC designs. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. Collaborate with RTL designers to ensure seamless integration of DFT features i...

In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 4 to 10 years of experience in RTL designs. Deep knowledge of mixed signal concepts Deep knowledge of RTL design fundamentals Deep knowledge of Verilog and System-Verilog Deep knowledge of front-...

We are looking for a seasoned Senior Design Verification Engineer with 8+ years of experience in verifying complex digital IPs and SoCs. The ideal candidate will have strong expertise in developing UVM-based verification environments and driving functional coverage closure. Key Responsibilities: Develop and maintain constrained-random and directed testbenches using System Verilog/UVM Define verification plans and test strategies based on specifications Write test cases, checkers, and functional coverage models Perform RTL simulations, debug failures, and ensure coverage closure Collaborate with RTL, DV, and firmware teams across verification lifecycle Support gate-level simulation, regressio...

RoleSenior CAD Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Ident...

RoleASIC CAD Lead Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a ASIC CAD Lead Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools...

RoleFront-End RTL Design Automation Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load dis...

Role: RTL Design Engineer Experience: 10+years Notice Period: Max 15days preferred Role Overview We are looking for a RTL Design Engineer? to deploy andsupport our front-end tools, to develop scripts to automate regression anddebug flows, and to work along with our design, implementation and verificationteams. What you'll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and priori...

As a RTL Packet Processing Engineer at Eridu AI India Private Limited, a subsidiary of Eridu Corporation, you will be instrumental in shaping and executing cutting-edge Networking IC solutions. Your primary tasks will include: - Designing and architecting solutions for high-speed networking devices with a focus on latency optimization, QoS support, CAMs, and routing tables. - Implementing designs on ASIC platforms, ensuring adherence to industry standards and performance benchmarks, and conducting comprehensive testing and validation. Your responsibilities will also involve: - Analyzing and optimizing pipelining architectures to enhance performance metrics. - Providing support for various ne...

Job Requirements • An expert level experience with PCIe/CXL IP/sub-systems. • Highly experienced with defining block, sub-system and SOC top level test plans. • An expert level with developing UVM-based SV test-benches. • Deep understanding and knowledge of verification methodologies flows and quality metrics. • Great debugging and problem-solving skills. • Team player with great interpersonal communication skills. Job Qualifications • At least 5 years of relevant experience in PCIe/CXL verification. • Strong and relevant expertise with ASIC simulation tools and advanced verification methods. • Expert level in verification languages such as UVM and System Verilog. • Relevant experience with ...

Job Requirements • An expert level experience with PCIe/CXL IP/sub-systems. • Highly experienced with defining block, sub-system and SOC top level test plans. • An expert level with developing UVM-based SV test-benches. • Deep understanding and knowledge of verification methodologies flows and quality metrics. • Great debugging and problem-solving skills. • Team player with great interpersonal communication skills. Job Qualifications • At least 5 years of relevant experience in PCIe/CXL verification. • Strong and relevant expertise with ASIC simulation tools and advanced verification methods. • Expert level in verification languages such as UVM and System Verilog. • Relevant experience with ...

Roles & Responsibilities: • To be part of a highly skilled ASIC Team working on the newest technology nodes • Responsible for overall IP/Block and sub-system verification from test plan creation, SystemVerilog/ UVM testbench development to signoff • Ensure first pass product through multi-dimensional verification coverage including mixed mode verification • Mentoring and coaching junior team members • Pair with similar domain specialists across other geographical locations on core technical initiatives Skills required: • Should have expertise in IP/Block/Subsystem level verification and AMBA protocols-APB/AHB/AXI. • Proven track record of building test plan, UVM Environment and test benches ...

Role & responsibilities: Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Core Requirements Basic understa...

Role & responsibilities Bachelors with 2+ years of work experience or Post Graduate Degree in Electronics Engineering or related engineering field with 1-2 years of working experience is required. Description: Good knowledge of Basic Analog/Digital concepts. • Good knowledge of Verilog/SV concepts. • Experience in using spice simulation and digital simulation tools like Virtuoso, primesim, Finseim, Hspice, Xcellium, Simvision, Waveview. • Experience in understanding Spice simulation environment/Digital simulation environment, able to debug analog/digital design related issues. • Work experience in co-sim simulation designs is a plus. • Good scripting skills using perl, python is a plus. • Mu...

Dear Candidate's, find the below Details & JD Location: Hyderabad NP: Immediate-15 Days Experience: 3-5 Years(02 Positions) 5-7 Years(01 Position) interview: 03 Rounds Job Description: Good understanding of digital / mixed signal circuits and experience in Digital /Mixed signal Verification. Understand the usage of tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice. • Hands on experience in writing Verilog, Real Number Models is a plus. • Hands on experience in building SV testbenches at Block and Fullchip Level. • Hands on experience in SV, UVM based Verification. Good scripting skills using perl, python is a plus. • Previous work experience in DRAM memory related fie...

Role & responsibilities : * Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy. * Test Case Development: Develop stimulus and test cases to increase the functional coverage for DRAM, SRAM, and other emerging memory technologies. Core Requirements: * Strong Communication Skills: Ability to collaborate effectively within a team. * Leadership: Guide new team members and engineers, sharing your knowledge and experience. * Analytical Expertise: Deep understanding of complex CMOS and/or gate-level circuit designs. * Proficiency in SPICE and/or Verilog simulations. Preferred candidate profile : Required Skills: * Experience with SystemVeril...

Job Title: ASIC Engineer (Entry to Mid-Level) Job Description: We are seeking motivated ASIC Engineers to join our dynamic team. This role encompasses a range of responsibilities from foundational verification to physical design and synthesis. The ideal candidate will have a solid understanding of Verilog and SystemVerilog, with a keen interest in expanding their knowledge in ASIC design and verification. Responsibilities: Develop and verify ASIC designs using Verilog, SystemVerilog, and UVM methodologies. Perform RTL design and SOCC verification. Execute RTL synthesis to optimize performance, power, and area. Develop and implement timing constraints for functional and test modes. Participat...

Description: As a Design Verification Engineer, you will work with a highly innovative and motivated design team using state of the art memory technologies to develop the most advanced DRAM and Emerging memory products. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high-speed designs, complex functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies. You will need to have the ability to work as a Design Verification Engineer, to evaluate Full chip or block level functionality and provide solut...