500 System Verilog Jobs - Page 10

verification experience in SV, UVM, DDR, serdes high speed protocol, PCIE

In your new role you will: Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices. Responsible for: Designing self-checking test benches using modern verification techniques o Implementing functional coverage and assertions using System Verilog and UVM. Developing TB environment using SV and UVM. Developing test and functional coverage plans based on device specifications. Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes. Your Profile You are best equipped for this task if you have: Engineering in Electrical/electronic streams , or equivalent experience. 7+ years experience in constrained-random, coverage driven verification environments. Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology). Expertise in Gate Level simulations (GLS) a nd have debugged, root caused real netlist issues. A solid understanding of verification concepts and experience designing class-based test benches. C coding, Formal verification methods and Power aware simulation will be an advantage Excellent written and oral communication skills Strong debugging skills, functional simulations and GLS simulations.

Qualifications and Preferred Skills: BS, MS in Electrical Engineering, Computer Engineering or Computer Science. 8+ years and current hands-on experience in microarchitecture and RTL development . Proficiency in Verilog, System Verilog . Familiarity with industry-standard EDA tools and methodologies. Experience with large high-speed, pipelined, stateful designs, and low power designs. In-depth understanding of on-chip interconnects and NoC's. Experience within Arm ACE/CHI or similar coherency protocols. Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's. Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus. Experience with modern programming languages like Python is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills.

nikita.chaudhary@enlink.com Job Title: Design Verification Engineer SoC/IP Verification Location: Bangalore Job Type: [Full-Time] Experience : 5 to 9 Years Job Description: We are looking for experienced Design Verification Engineers with a strong background in SoC and IP-level verification. The ideal candidate will be responsible for developing and implementing advanced verification environments and ensuring the functional correctness of complex digital designs. Key Responsibilities: Develop and maintain verification environments for SoC and IP designs Implement test bench components and verification infrastructure Create and execute test cases to ensure thorough validation of designs Develop and track functional coverage metrics Write and integrate assertions for design verification Perform failure analysis and debug issues efficiently Work with high-speed interface protocols such as PCIe Gen6, CXL,Ethernet, and UCIe Required Skills: Strong experience in SystemVerilog/UVM-based verification methodologies Solid understanding of digital design and verification flows Proven skills in debugging and failure analysis Experience with functional coverage and assertions Hands-on experience with at least one of the following protocols:PCIe Gen6, CXL, Ethernet, or UCIe Excellent communication and teamwork skills Preferred Qualifications: Bachelors or Masters degree in Electronics, Electrical, or relate engineering disciplines Exposure to scripting languages (Python, Perl, etc.) for automation Contact HR Nikita Chaudhary 8879637539 nikita.chaudhary@enlink.com

Qualifications and Preferred Skills BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8+ years and current hands-on experience in block-level/IP-level/SoC-level verification. Proficiency in Verilog, System Verilog . Familiarity with industry-standard EDA tools for simulation and debug. Deep experience with UVM-based test benches. Experience with modern programming languages like Python . Knowledge of Arm AMBA protocols such as AXI, APB, and AHB. Understanding of Arm CHI protocol is a plus. Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs. Experience with formal verification techniques, emulation platforms is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills.

Application Engineering, Sr.Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10306 Remote Eligible No Date Posted 27/03/2025 Alternate Job Titles: Transistor Level Verification Engineer Custom Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A motivated, self-starter Application Engineer with a passion for custom circuit verification and technology. You have a strong technical background in engineering, particularly in the field of transistor-level custom design verification. You excel at understanding circuits at the SPICE netlist level and design descriptions in Verilog/System Verilog. Your knowledge of transistor-level design and simulation in MOSFET technology sets you apart. You thrive in both independent and collaborative settings and have excellent communication skills that enable you to discuss, collaborate, and present product information effectively. Ideally, you also have experience in memory design and verification, which enhances your ability to support our industry-leading ESP equivalence check product. What You ll Be Doing: Working closely with customers to understand their requirements in verifying custom design IP. Tailoring solutions to address challenging verification scenarios for custom designs. Collaborating with the product team to define, test, and deploy new features. Providing technical support and expertise on Synopsys ESP equivalence check product. Conducting product demonstrations and training sessions for customers and partners. Developing and maintaining technical documentation and application notes. The Impact You Will Have: Enhancing customer satisfaction through effective technical support and custom solutions. Driving the adoption and integration of Synopsys ESP equivalence check product. Contributing to the continuous innovation and development of new product features. Ensuring the highest quality of custom designs by catching elusive corner case design inconsistencies. Building strong relationships with customers and fostering long-term collaborations. Expanding Synopsys market presence through successful customer engagements. What You ll Need: Bachelor s or Master s degree in Engineering/Technology (Electronics/Electrical or related field). 1-2 years of experience in custom design verification. Understanding of circuits at SPICE netlist level and design description in Verilog/System Verilog. Knowledge of transistor-level design and simulation in MOSFET technology. Excellent written and oral English communication skills. Who You Are: A proactive and driven individual with a keen interest in custom circuit verification. You are a team player who enjoys both independent and collaborative work environments. Your strong communication skills enable you to convey technical concepts effectively. You are adaptable, detail-oriented, and thrive in a fast-paced, dynamic environment. Your commitment to continuous learning and improvement drives your success in the field of application engineering. The Team You ll Be A Part Of: You will be a key member of our ESP team, which focuses on developing a differentiated custom equivalence check solution. Our team is dedicated to constant innovation and developing new capabilities to meet the evolving needs of our customers. We collaborate closely with R&D and product engineering to define, test, and deploy new features, ensuring our technology remains at the forefront of the industry. Join our diverse and dynamic team to drive innovative technical solutions and contribute to the success of our advanced features portfolio. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Responsibilities: Build and guide a team of DFT engineers to deliver the architecture and the DFT deliveries towards SOC development. Engage with the RTL & physical design program management to plan and execute the DFT deliveries. Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise : At least 10+ years of experience in DFT implementation / methodology Strong understanding of digital design and test principles. Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion Experience with EDA tools , Synopsys and Cadence &scripting languages (e.g., Python, TCL). Knowledge of IC design flows, verification tools, and fault models Ability to identify, analyze, and resolve testing challenges. Work effectively within multidisciplinary teams, communicating complex technical details clearly. Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards. Technically lead/managed 10 - 15 DFT engineers to deliver DFT implementation on SOC Preferred technical and professional experience NA

We are looking for a talented and highly motivated research scientist to help advance our efforts in AI4Code, specifically focusing on testing and validation. In this role, you will work at the intersection of AI, software engineering, and testing, leveraging state-of-the-art techniques to enhance automated code analysis, test generation, and defect detection. You will collaborate with a multidisciplinary team to develop and deploy AI-driven solutions that improve software quality, reliability, and maintainability. Required education Doctorate Degree Preferred education Doctorate Degree Required technical and professional expertise Deep expertize in program analysis, formal verification. Proficiency in Python, Java, or other relevant programming languages. Familiarity with machine learning, NLP, or AI-driven software analysis. Experience with test frameworks, static analysis tools, or automated testing methodologies. Solid understanding of data structures and algorithms to enhance test generation and analysis. Passion for AI-driven innovation in software engineering Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

DESIRED PROFILE : Expertise in working with large teams working on ASIC verification or digital verification Expertise in Digital Verification / Formal Verification flow Expertise in working on system Verilog assertions & test benches Expertise in working on UVM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim, Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath, DSP based ASICs Good knowledge in gate-level simulation, and Scripting languages like Python, TCL JOB SPECS : Responsible to perform Digital Verification / Formal Verification flow Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire, build technical teams from scratch and manage high caliber technical teams across GCC, ODC and onsite. Must be willing to work at customer sites as per customer needs Must be willing to travel worldwide at short notice as per customer needs Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners.

Senior/ Lead - Design Verification Engineer SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Experience with python or any other scripting language is a plus Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. BSEE/BS Computer Science, Computer Engineering, Electrical Engineering (or equivalent). Good Experience on Semiconductor/VLSI Design verification IP's. Experience with ISO 26262 is plus Leads must have Faultsim experience Z01X tool experience and any equivalent tool Can consider GLS experience for rest of the engineers. Location: Bangalore / Hyderabad Notice Period: Immediate to 60 days. Experience: 4 to 12 Years

Greetings from Synopsys!!! I hope this message finds you all well! At Synopsys Inc, we are looking for Senior Design Verification Engineer and expertise in System Verilog and UVM methodology skills for an exciting project. If you're open to exploring this opportunity, I would love to discuss it further. Please feel free to reply to this email or we can chat over the phone at your convenience. I believe this could be a great match for both of us. Experience: 5+yrs to 15years Location: Bengaluru & Noida Expertise in UVM/OVM/SOC and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for verification projects using VMM/OVM/UVM methodologies . Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Taufiq Hussain Talent Acquisition, Sr Staff | People | mobile: +91 9148401555 | email: taufiq@synopsys.com

The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Digital Systems IP team within the Engineering Enablement organization. The IP team builds, curates and guides the development of IP across ADI. we're seeking a highly experienced, seasoned DV expert with experience in leading DV efforts for verification of different IP components, subsystems from scratch. About the role In this position the successful candidate will be exposed to the entire product lifecycle from concept phase, through design, verification, implementation, and release of IP to various product teams. They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products. This is a senior role with the opportunity to create real impact within the organization and build a promising career. Responsibilities Verification of complex Digital designs and sub-systems using leading edge verification methodologies. Architecting a unified verification testbench environment Defining verification strategy, testplans, tests and verification methodology for chip-level verification. Working with the design team in generating test-plans and closure of code and functional coverage Technically mentoring verification engineers on SoC Verification responsible for block/IP-level DV Continuous interaction with Design, Architecture and Firmware teams Tracking and management of design verification improvements Required Qualifications Bachelors or masters degree, in Engineering (Electronic Engineering) or equivalent. 15 years ASIC design verification or related work experience. Leadership skills enabling one to define and implement a verification strategy Demonstrated ability to communicate with peers, managers, and project stakeholders effectively using both verbal and written communications Proficient in developing unit and SoC level test benches using UVM Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology, formal verification Behavioral modeling of analog blocks, System Verilog Real-Number Modeling, behavioral model validation and mixed-signal simulators like Cadence Xcelium Working with processors Gate Level Simulation (GLS) verification flow for SoC verification. Verilog, C/C++, System C, Java, TCL/Perl/Python/shell-scripting Experience in Property Specification Language (PSL), Matlab (including for co-simulation and HDL generation) and digital signal processing would be a plus Low power methodologies such as CPF/UPF Excellent interpersonal and communication skills and the dream to take on diverse challenges Self-motivated and enthusiastic

In this role, he/she would be responsible for verification of GPU Design by meeting the demands of the constantly evolving project schedule. The successful candidate will be a member of the GFX team. He/she will demonstrate passion towards design, design verification, be a teammate, a problem solver with independence, creativity, and interpersonal skills. Working with all partners such as lead architects and block design teams to understand features to be implemented and verified. Developing robust test plan for both synthetic testing and real workload trace Debug verification test failures, working with the verification team to accurate defects. Make sure AMD next generation GFXIP can meet performance/power/function expectation. Requirements: Must have Min 8 years of experienced in ASIC verification. Must be proficient in Verilog and System Verilog language Must be good at optimizing timing in digital design. Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and develop optimal microarchitecture specification that meets PPA goals. Be proficient of script language like Perl, Python. Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail. Must have good English hearing, speaking, reading, and writing capabilities. Must have good teamwork and interpersonal skills. Graphics pipeline experience is preferred. Good knowledge of computer architecture is preferred. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required. Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering / Computer Engineering with Digital Systems/VLSI as major with 8+ Years of Exp

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com . www.silabs.com Meet the team: The Baseband Modem Design group, in HYD, is primarily responsible for designing and developing cutting-edge WIFI modem solutions which are integrated into low-power/line-powered SoCs used in Wireless-IOT products. The group is responsible for the RTL implementation of the new WIFI standards required in the IOT space market. The team actively collaborates with signal processing experts in defining the algorithms and implementing them. The team also verifies core modem functionality and works with extended Verification team to verify all the System level usecases involving the baseband modem. It also handles the pre-Si and post-Si validation. Responsibilities: Develop complex communications or signal processing blocks for wireless-IOT products. Understanding of OFDM/signal processing is strongly desired Collaborate with System Engineers to drive the definition of wireless blocks to meet product requirements. Proficiency in Matlab/C is strongly preferred Micro-architecture and RTL design of modules using Verilog/System Verilog HDL coding, adhering to quality standards. Prepare and hold Architecture, Design, and Verification reviews with technical staff throughout project lifecycle Pre-silicon verification utilizing a combination of block/chip-level test benches. Validation/bring-up of designs on silicon, providing support to cross-functional teams Apply Low-power digital circuit design concepts Skills required: Demonstrated ability to work with Systems team to micro-architect and design complex digital subsystems Understand Matlab algorithm implementation and translate to effective RTL micro-architectures Verilog RTL design with demonstrated experience of taking designs through the silicon development lifecycle to production Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers (like vc, Questasim), and power analysis tools Experience with logic synthesis, timing constraints and timing closure Experience in working with backend team to optimize design for power performance and area Experience with scripting and automation. Knowledge of Python, Perl, and Tcl Experience with revision control and configuration management systems (such as Perforce, Git, Methodics) Excellent written and verbal communications skills Demonstrated ability to generate high output in a self-driven manner Experience Level: 4-6 years in Industry Education Requirements: Master s /Bachelors degree in Communications/Electronics Engineering Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support #LI-DK1 #LI-Hybrid Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

Job Summary: We HCL TECH are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 4-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SENIOR VERIFICATION ENGINEER – SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware Location - Bengaluru,Chennai,Hyderabad,Noida

Emulation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: should have emulation experience working on available platforms such as; Palladium, Veloce, or Zebu, as well as experience with compilation, debug, performance, and throughput tuning Experience using Verilog, VHDL design Experience with C/C++ and System Verilog, UVM verification environments Experience writing scripts using Perl, Python, Makefile Debugging experience using tools like waveform, Verdi, Simvision Strong communication skills and ability to work as a team Description You’ll support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). You’ll be bringing up SOCs on emulation, root causing SoC/Processor test fails and emulator environment issues. – We are in constant collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams. – Your strong design, debug, communication, and teamwork skills will be essential. – You will also work with leading emulation vendors to debug issues. Skills Experience Zebu Verilog, Python Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

TECHNICAL LEAD – DFT SmartSoC is looking for a smart and enterprising leader with expert knowledge in DFT to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking. You will be responsible for leading and managing a team, client communication, and project execution. Job Responsibilities- Lead an internal DFT team, executing projects for an offshore client Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 7+ years of experience in DFT, mainly Scan Architecture, ATPG & MBIST Experience in planning scan chains, running scan insertion flow Experience in latest Cadence tool set Genus & Modus Experience in ATPG for Stuck@, TFT, IDDQ & Path delay faults with tough coverage targets Experience in MBIST architecture, generation and implementation Experience in AECQ100 requirement standard is a big plus Experience in working with a multi-site team is a big plus Experience in working on critical time-bound projects is a big plus Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of DFT team, you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in processor flow and post silicon validation

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment