Posted:2 days ago|
Platform:
Work from Office
Full Time
PCIe Design Verification Engineer (Peripheral Component Interconnect Express)
Perform functional and compliance verification of PCIe-based SystemC IPs and subsystems.
Integrate SystemC PCIe IP/Subsystem in Avery PCIe VIPs and utilize for protocol-level verification.
Debug complex issues across transaction, data link, and physical layers of PCIe.
Analyze and interpret PCIe specifications for test planning and coverage.
Work closely with design, architecture, and validation teams to ensure feature completeness and spec compliance.
Generate and review verification plans, test reports, and coverage metrics.
Strong hands-on experience with Avery PCIe VIP (integration, debug, customization).
In-depth knowledge of PCIe protocol (Gen4/Gen5 or higher).
Solid experience in System Verilog / UVM methodology.
Strong debug and problem-solving skills using simulators like Questa, VCS, or Xcelium.
Familiarity with coverage-driven verification and constraint random testing.
Good understanding of verification flow, regression setup, and scripting (Python/Perl/Shell).
PCIe, Verilog, SV, UVM
Shifastar Technologies
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