Design Verification Engineer (Power Management)

Your role and responsibilities
Understand the design specification , TB architecture Learn in IBM Fusion and Trek verification languages and tools, apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise 8+ years of work experience in IP, Sub-system & SOC level - Exp in creating multiple UVM/SV based env from scratch, Strong in Block Level verification Exp in developing checkers, Scoreboards, Monitors, Test plan development, Code coverage, Functional coverage, FSM based design, System Verilog Assertions. Protocols SPI (Serial Peripheral Interface), AXI, AHB, APB, ETHERNET, I2C, JTAG, UART Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Preferred technical and professional experience Worked on Power Management blocks , Low Power, Boot & Reset sequences Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug