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Design Verification Engineer (Power Management)

Design Verification Engineer (Power Management)

IBM

8 - 13 years

6 - 10 Lacs

hyderabad

Posted:3 hours ago| Platform:

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Skills Required

soc system verilog ip uvm fusion soc verification c++ design verification vhdl sub-system rtl design axi fpga solid works rtl coding debugging perl asic asic verification sv ovm rtl spi verilog ethernet product design pcie vlsi logic design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Understand the design specification , TB architectureLearn in IBM Fusion and Trek verification languages and tools, apply them successfullyDevelop the verification environment and test benchDebug fails using waveform, trace tools and debug RTL codeWork with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of work experience in IP, Sub-system & SOC level - Exp in creating multiple UVM/SV based env from scratch,Strong in Block Level verificationExp in developing checkers, Scoreboards, Monitors, Test plan development, Code coverage, Functional coverage, FSM based design, System Verilog Assertions.Protocols SPI (Serial Peripheral Interface), AXI, AHB, APB, ETHERNET, I2C, JTAG, UARTHardware debug skills backed by relevant experience on projectsExposure in developing testbench environment, write complex test scenariosGood communication skills and be able to work effectively in a global team environment Preferred technical and professional experience Worked on Power Management blocks , Low Power, Boot & Reset sequencesScripting Expertise backed up relevant experience in the sameWriting Verification test plansFunctional and code coverage analysis and debug

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Design Verification Engineer (Power Management)