Posted:1 hour ago|
Platform:
Work from Office
Full Time
Were looking for a talented GLS (Gate-Level Simulation) Verification Engineer with strong experience in verifying complex SoCs using industry-standard tools and methodologies.
* Hands-on experience in GLS verification using Cadence Xcelium (mandatory) and Synopsys VCS.
* Minimum 3 years of GLS experience with a solid understanding of gate-level verification flows.
* Good understanding of physical design concepts relevant to GLS verification.
* Strong knowledge of SystemVerilog and UVM-based testbench environments.
* Experience with DDR or HBM PHY GLS will be an added advantage.
* Basic understanding of SoC design and common bus protocols (AMBA, AXI, AHB) is a plus.
Proxelera
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