3.0 - 8.0 years

8 - 18 Lacs

bengaluru

Work from Office

Job Description: Were looking for a talented GLS (Gate-Level Simulation) Verification Engineer with strong experience in verifying complex SoCs using industry-standard tools and methodologies. Key Responsibilities & Skills: * Hands-on experience in GLS verification using Cadence Xcelium (mandatory) and Synopsys VCS. * Minimum 3 years of GLS experience with a solid understanding of gate-level verification flows. * Good understanding of physical design concepts relevant to GLS verification. * Strong knowledge of SystemVerilog and UVM-based testbench environments. * Experience with DDR or HBM PHY GLS will be an added advantage. * Basic understanding of SoC design and common bus protocols (AMBA,...

Posted 3 weeks ago

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Senior Design Verification Engineer- Lead and above Tessolve

5.0 - 10.0 years

5 - 11 Lacs

hyderabad, bengaluru

Work from Office

Position: Sr.Design Verification Engineer-Lead and above Experience: 5+ years to 30 years Location - Bangalore/Hyderabad Notice period: immediate to 30 days most preferable. Position Description: To be part of a highly skilled ASIC Team working on the newest technology nodes Responsible for overall IP verification from test plan creation, UVM development to signoff. Pair with similar domain specialists across other geographical locations on core technical initiatives SKILLS required: Good knowledge of System Verilog TB, UVM Methodology, Debug and VIP Development Exposure of SERDES/UNIPRO/PCIE/UFS/DDR protocols is an advantage Exposure to verification of complex high speed PHY Proven track re...

Posted 1 month ago

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GLS Verification Professional TekWissen

3.0 - 8.0 years

5 - 10 Lacs

Bengaluru

Work from Office

GLS Verification Create or modify testbenches compatible with gate-level netlists. Set up timing annotations using SDF (Standard Delay Format) files. Configure simulation tools (like VCS, ModelSim, or Xcelium) for GLS.

Posted 5 months ago

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GLS Verification Engineer Kaizen SRA Technologies Private Limited

6.0 - 15.0 years

4 - 8 Lacs

Hyderabad / Secunderabad, Telangana, Telangana, India

On-site

Experience range : 6-15 Yrs Location : Hyderabad Availability : Immediate 30 days GLS Verification | Job Description : Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Collaborate with cross-functional teams to define and execute gate-level simulation test plans. Develop and implement gate-level simulation strategies for complex digital designs. Conduct gate-level simulations to verify the functionality and performance of digital designs. Work closely with design and verification teams to identify and resolve issues at the gate level. Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process. Ensure compliance with industry stan...

Posted 5 months ago

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