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3.0 - 7.0 years

3 - 5 Lacs

Sriperumbudur, Chennai

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Good operating and setting knowledge in VMC,HMC & HBM Makino & Doosan machine Benefits : Accommodation free of cost ,Food 50% subsidy For 3 Times, Double OT, Esi,Pf,Bonus,Gratuity,Etc. PMAC.PVT.LTD Contact : HR - 9566947765 , hr@pmacindia.com Role & responsibilities

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2.0 - 7.0 years

2 - 5 Lacs

Devanahalli, Bengaluru, peenay

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Hi All, We are hiring for MNC company Randstad India Pvt Ltd ( Bangalore Peenya Location ) We are looking for ITI & Diploma ( Mechanical & tool & Die Making ). Gender - Male, Education - ITI & Diploma ( Mechanical & tool & Die Making ). Experience - 1 to 10 Years Salary: 15% to 20% Hike based on Interview ). Benefits: PF, ESIC, & Transport, Shift Timings: 8 Hours work ( Rotational shifts ) 6 days working (Monday Saturday) Interview Mode - Face to Face interview. Job Profile: We have openings for CNC, VMC, VMC Double Column Operator, VMC Programmer, CNC Turning operator, CNC VTL Incharge - with programming capability, CNC VTL Operator. EDM & Wire Cut Operator Venkateswarlu K 9676590526 venkateswarlu.k@randstad.in

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7 - 10 years

35 - 60 Lacs

Hyderabad

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Senior Analog Manager /Manager /Lead ( HBM / IO ) www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Sevya is an innovative semiconductor design company dedicated to pushing the boundaries of technology. We focus on developing cutting-edge solutions that empower the electronics industry. Our mission is to drive the future of technology, and we are seeking talented individuals to join our dynamic team. Job Description: Sevya is architecting and designing a HBM transceiver in advanced FinFET node. Sevya needs analog designers at all levels with skills in the areas of analog circuit design, custom digital design for SerDes and other high speed IP applications, signal and power integrity modeling, pre and post silicon debug. Familiarity with HBM, DDR and other memory standards in highly desirable but not necessary if the candidate has good knowledge of high speed design. Candidates with experience of linear circuits such as high bandwidth LDOs, amplifiers, charge pumps etc. who want to explore high speed design are also welcome, we have appropriate work and there will be opportunities to learn more. Specifically we are looking for people with approximately 10-15 yrs of experience for Senior mnager positions and 7-10 yrs for lead positions. Candidates with higher experience also welcome for appropriate role. Responsibilities: I/O Architecture Design: Develop and design the input/output architecture for integrated circuits using HBM technology. Signal Integrity Analysis: Perform signal integrity analysis to ensure reliable and high-speed data transfer between the HBM memory and the rest of the system. Circuit Design: Design and optimize circuits for HBM I/O interfaces, considering factors such as power consumption, area, and performance. Collaboration: Work closely with cross-functional teams, including system architects, memory designers, and layout engineers, to ensure seamless integration of HBM I/O interfaces into the overall system. Standards Compliance: Ensure that HBM I/O designs comply with industry standards and specifications, such as JEDEC standards for high-bandwidth memory. Simulation and Modeling: Utilize simulation tools and models to validate the design's performance and address any potential issues related to signal integrity, power delivery, and thermal considerations. Debugging and Troubleshooting: Identify and resolve issues during the testing and debugging phases of the design process. Documentation: Prepare detailed documentation of the HBM I/O design, including specifications, test plans, and design guidelines. Requirements: Bachelor's degree or higher in Electrical Engineering or a related field. A minimum of 7-15 years of experience in analog circuit design within the semiconductor industry. Proven expertise in designing analog blocks, including Bandgap references, PLLs, LDOs, and High-Speed I/O circuits. Proficiency in industry-standard Electronic Design Automation (EDA) tools for analog design and simulation. Strong knowledge of semiconductor fabrication processes and technologies. Exceptional problem-solving and analytical skills. Effective communication and teamwork abilities. Preferred Qualifications: - Experience in mixed-signal circuit design. - Familiarity with high-speed data communication interfaces. - Knowledge of low-power design techniques. - Published research or patents related to analog design. Why Join Us: Sevya is committed to creating an environment of innovation, professional growth, and collaboration. As an I/O Design Engineer, you will be a part of groundbreaking projects and a team that values creativity and excellence. We offer competitive compensation, benefits, and the opportunity to be a driving force in the future of semiconductor technology. If you are an ambitious Analog Design Engineer eager to push the boundaries of analog design and help shape the future of technology, we encourage you to apply. Join us in our mission to redefine what's possible in the world of electronics! Skills: Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

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10 - 15 years

50 - 80 Lacs

Hyderabad

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Senior Analog Manager /Manager /Lead ( HBM / IO ) www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Sevya is an innovative semiconductor design company dedicated to pushing the boundaries of technology. We focus on developing cutting-edge solutions that empower the electronics industry. Our mission is to drive the future of technology, and we are seeking talented individuals to join our dynamic team. Job Description: Sevya is architecting and designing a HBM transceiver in advanced FinFET node. Sevya needs analog designers at all levels with skills in the areas of analog circuit design, custom digital design for SerDes and other high speed IP applications, signal and power integrity modeling, pre and post silicon debug. Familiarity with HBM, DDR and other memory standards in highly desirable but not necessary if the candidate has good knowledge of high speed design. Candidates with experience of linear circuits such as high bandwidth LDOs, amplifiers, charge pumps etc. who want to explore high speed design are also welcome, we have appropriate work and there will be opportunities to learn more. Specifically we are looking for people with approximately 10-15 yrs of experience for Senior mnager positions and 7-10 yrs for lead positions. Candidates with higher experience also welcome for appropriate role. Responsibilities: I/O Architecture Design: Develop and design the input/output architecture for integrated circuits using HBM technology. Signal Integrity Analysis: Perform signal integrity analysis to ensure reliable and high-speed data transfer between the HBM memory and the rest of the system. Circuit Design: Design and optimize circuits for HBM I/O interfaces, considering factors such as power consumption, area, and performance. Collaboration: Work closely with cross-functional teams, including system architects, memory designers, and layout engineers, to ensure seamless integration of HBM I/O interfaces into the overall system. Standards Compliance: Ensure that HBM I/O designs comply with industry standards and specifications, such as JEDEC standards for high-bandwidth memory. Simulation and Modeling: Utilize simulation tools and models to validate the design's performance and address any potential issues related to signal integrity, power delivery, and thermal considerations. Debugging and Troubleshooting: Identify and resolve issues during the testing and debugging phases of the design process. Documentation: Prepare detailed documentation of the HBM I/O design, including specifications, test plans, and design guidelines. Requirements: Bachelor's degree or higher in Electrical Engineering or a related field. A minimum of 7-15 years of experience in analog circuit design within the semiconductor industry. Proven expertise in designing analog blocks, including Bandgap references, PLLs, LDOs, and High-Speed I/O circuits. Proficiency in industry-standard Electronic Design Automation (EDA) tools for analog design and simulation. Strong knowledge of semiconductor fabrication processes and technologies. Exceptional problem-solving and analytical skills. Effective communication and teamwork abilities. Preferred Qualifications: - Experience in mixed-signal circuit design. - Familiarity with high-speed data communication interfaces. - Knowledge of low-power design techniques. - Published research or patents related to analog design. Why Join Us: Sevya is committed to creating an environment of innovation, professional growth, and collaboration. As an I/O Design Engineer, you will be a part of groundbreaking projects and a team that values creativity and excellence. We offer competitive compensation, benefits, and the opportunity to be a driving force in the future of semiconductor technology. If you are an ambitious Analog Design Engineer eager to push the boundaries of analog design and help shape the future of technology, we encourage you to apply. Join us in our mission to redefine what's possible in the world of electronics! Skills: Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

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7 - 12 years

40 - 75 Lacs

Bengaluru

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Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Staff Design Verification Engineer Job Description In this role you will be responsible Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role And Responsibilities Partner with Architects and RTL Design team to grasp high-level system requirements and specifications. Formulate comprehensive test and coverage plans to match the Architecture and micro-architecture. Define and implement a verification methodology that supports scalability and portability across various environments spanning including post-silicon. Develop the verification environment and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics. Create verification plans and develop testbenches tailored to assigned IP/Subsystem or functional domain. Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures. Support post-Si bring-up and debug activities. Track and communicate progress in the DV process by using key metrics like bug tracking and coverage reports. Requirements Bachelors or Masters degree in Electrical or Computer Engineering/Science Strong Architecture domain knowledge in x86/ARM CPU, or Memory, Coherency, Virtualization or Performance areas. Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 7yrs+ hands-on experience in IP/sub-system and/or SoC level verification Hands on experience and expertise with industry standard verification tools for simulation and debug (Questa/VCS, Visualizer) Experience using random stimulus along with functional coverage and assertion based verification methodologies a must. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation. Preferred Qualifications: Experience in development of UVM based verification environments from scratch. Hands on expertise and protocol knowledge in any of: APB/AXI/CHI, JTAG/I3C/SPI, , DDR5/LPDDR5/HBM, PCIE/CXL/UCIE/Ethernet compliance testing

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6 - 11 years

15 - 30 Lacs

Chennai, Bengaluru, Hyderabad

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Job Title: RTL Design Verification Lead & Manager Location: Bangalore Job Type: Full-Time Payroll: Direct Payroll Experience: 6 to 12 Years Work Mode: Work From Office Interview Mode: Virtual Interview Notice Period: 0-30 days preferred For Manager roles, a minimum of 8+ years of relevant RTL verification experience is required. Job Summary: We are looking for highly skilled RTL Verification Leads and Managers to join our motivated verification team. The selected candidates will play key roles in IP verification, with a focus on protocols such as UCIe, HBM, PCIe, AXI/ACE, Ethernet, DDR, and more. This position requires deep expertise in advanced verification methodologies and a strong background in RTL verification. Key Responsibilities: Lead and execute RTL verification tasks for IPs like UCIe, HBM, PCIe, and Bus Logic. Implement advanced verification methodologies such as UVM/OVM/VMM/SystemVerilog. Generate constrained random stimulus and perform assertion-based verification and functional coverage. Oversee register verification standards and manage NLP/GLS verification flows. Conduct IP and sub-system level verification for protocols including PCIe, UCIe, and HBM. Facilitate controller interoperability testing at the sub-system level. Qualifications: BE/ME/MTech/MS in Electrical Engineering or a related field. 6 to 12 years of RTL verification experience. Proficiency in UVM/OVM/VMM/SystemVerilog. Strong knowledge of constrained random stimulus generation, assertion-based verification, and functional coverage techniques. Experience with register verification standards and NLP/GLS verification flows. Hands-on experience in IP and sub-system level verification for protocols like PCIe, UCIe, and HBM is a strong plus. Prior experience in controller interoperability testing at the sub-system level is desirable. Note: Note: We are aiming to close this requirement soon so preference will be given to candidates who can join quickly.

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3 - 5 years

3 - 5 Lacs

Chennai

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VMC & HMC Operator with 2D Manual Programming Knowledge. accommodation FREE

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2 - 5 years

2 - 3 Lacs

Chennai, Kanchipuram

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CNC Machine Operator 1. Experience as a CNC Machine / ROBO Welding Operator. 2. Should have working experience of Heavy Industrial CNC Machineries & Component weight Upto 100 Kg. 3. Should have In-depth Knowledge in Programming, Reading & Understanding Engineering Drawings 4. Execution of production and checks as per the Control plans and Work Instructions issued. 5. Corrections of setups and adjustments in case of problems as per the advice of In-charge 6. Ensuring identification at the production stages 7. Maintaining Production Reports 8. Daily Machine Cleaning & Minimum Maintenance. Required Candidate profile 1. Candidate must be willing to relocate and work in Kanchipuram Location. 2. Candidate must be having 70% in DME with No History of Arrears 3. Hands-on Experience in cutting tools, Job setting, and Measuring Instruments. 4. Working Experience of Apprenticeship / NEEM Trainee will be considered.

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5 - 10 years

4 - 6 Lacs

Chennai

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To develop Programs for HMC / CNC HBM machines, prove out job. Hands on Experience in MasterCAM Software Preferred

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8 - 12 years

25 - 30 Lacs

Bengaluru

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The Datacenter Engineering Group (DPEA-SPIV) is seeking talented individuals for the role of Platform Validation Engineer to ensure platform quality. In this position, you will be responsible for driving the validation of both software and hardware on Intel server products, with a primary focus on Artificial Intelligence solutions, to guarantee the quality of software releases.Key Responsibilities: Lead platform-level validation across the full project lifecycle. Ensure comprehensive test coverage for one or more domains, including RAS, HBM, PCIe, and Memory. Own and drive the resolution of complex, multidisciplinary platform issues in collaboration with ingredient partners. Develop and maintain platform validation test plans and best-known methods (BKMs). Design and develop automation test scripts and validation utilities. Maintain high-quality bug tracking, including bug reproduction, monitoring aging trends, and ensuring thorough issue resolution. Conduct escape analysis and drive test coverage improvements in key validation domains (RAS, HBM, PCIe, Memory). Troubleshoot and resolve validation-related issues effectively. Demonstrate strong attention to detail and the ability to analyze complex data. Qualifications You should possess a Bachelor's or Master's degree in computer science, software engineering, or a related field and must have minimum of 8 years of experience in validation, with at least 2 years in a leadership role. Additional qualifications include: Basic Knowledge on artificial intelligence (AI) models and Machine learning (ML) concepts In-depth Knowledge on any one or more domains -RAS, HBM, PCIe, AI workloads, Memory. Hands-on experience in System/platform Validation and Basic Knowledge in Linux Kernel debugging. Demonstrated experience and skill in server platform validation and test case development. Must have experience in Python scripting and test content automation. Strong analytical problem solving, code debugging and module based problem-solving skills. Demonstrated capability to work within a team environment facing fast-changing requirements and complicated stakeholders Demonstrated effectiveness in multitasking over simultaneous problem areas and/or assignments Good team player, be able to work well with peers and seniors from various disciplines, employs good team practices Good customer orientation and ability to interface with customers and/or stakeholders from remote sites. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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5 - 8 years

1 - 3 Lacs

Bengaluru

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CNC Operator for a Horizontal Boring Machine with programming knowledge of Fanuc CNC Systems, thorough knowledge of understanding drawings, processes, and inspection procedures & good communication skills. Program and operate the machine.

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9 - 14 years

27 - 30 Lacs

Bengaluru

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Defines, develops, and performs SoC level power, thermal, and performance validation and optimization plan across Intel products. Understands the business implications of ensuring power and performance KPIs within target and power and thermal limitations. Drives SoC level usage optimization under specific scenarios, develops key performance indicators and landing zones, power and thermal benchmarks, and drives execution, reporting, and documentation of results. Ratifies optimizations from hardware/software architecture and proposes solutions to software PTP teams. Develops power, thermal, and performance validation methodologies, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs SoC level debug to identify root causes and resolves all functional and triage failures for power, thermal, and performance issues. Develops validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. Configures and sets up data logger for thermal data collection and analysis. Publishes SoC level power, thermal, and performance validation reports summarizing all validation and optimization activities performed, reviews results, and communicates to relevant teams. Works with architecture, design, verification, firmware, software, and platform teams to maintain and improve debug, validation test strategy, methodologies, and processes to ensure power, thermal, and performance meet and exceed product completive targets and specifications. Qualifications Minimum Requirements:- BE degree or ME degree with 9 years+ in Electrical/Electronic Engineering or closely related field Knowledge of object-oriented programming principles Experience in writing SW content in Python Hands on experience measuring electrical performance of analog signals using oscilloscopes, source meters, server SoC validation platforms, power and performance recipe, SOC max current, min voltage and di/dt measurements Excellent hands-on silicon and platform debug skills Experience writing and debugging software to control hardware Proven experience to work well in teams and provide strong independent contributions Additional Preferred Qualifications:- Experience validating power delivery systems at system level Experience analysing power delivery systems Expertise in one or more of the following domains: CPU benchmarks, Power management, Reset/Fuse, PCIe, Memory sub-system validation Knowledge of Computer System Architecture Experience with Memory, network adaptors, fabric architecture, HBM, Cache Coherency Experience with debug of Intel chipsets and/or CPUs Understanding of a subsystem HW/SW stack, including the silicon, all onboard HW components and connectors and devices, drivers, and applications In depth knowledge of control loops in non-isolated buck converter topology Experience writing Python code to automate test procedures Understanding of PCB layout best practices Understanding of statistical data analysis and design of experiments. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements. Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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1 - 6 years

2 - 5 Lacs

Bengaluru, peenay

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Hi All, We are hiring for MNC company Randstad India Pvt Ltd ( Bangalore Peenya Location ) We are looking for ITI & Diploma ( Mechanical & tool & Die Making ). Gender - Male, Education - ITI & Diploma ( Mechanical & tool & Die Making ). Experience - 1 to 10 Years Salary: 15% to 25% Hike based on Interview ). Benefits: PF, ESIC, & Transport, Shift Timings: 8 Hours work ( Rotational shifts ) 6 days working (Monday Saturday) Interview Mode - Face to Face interview. Job Profile: We have openings for CNC, VMC, VMC Double Column Operator, VMC Programmer, CNC Turning operator, CNC VTL Incharge - with programming capability, CNC VTL Operator. EDM & Wire Cut Operator Venkateswarlu K 9676590526 venkateswarlu.k@randstad.in

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