50 Hbm Jobs

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, you will be involved in utilizing industry-standard protocols and methodologies. Your proficiency in System Verilog and Verilog, along with a solid understanding of Object Oriented Programming, will be essential for this role. As a Senior/Lead ASIC Verification Engineer, you will have the opportunity to lead the development of reusable Verification environments for a minimum of 2 projects using VMM, OVM, or UVM methodologies. Your expertise in protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory protocol will be valuable. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development updates, and collaborating with Architects and methodology experts to address issues and enhance output from an architecture/methodology perspective. If you are a proactive and reliable professional with a passion for Verification, we encourage you to share your updated CV with us at taufiq@synopsys.com or refer individuals who would be interested in this opportunity. At Synopsys, we value and promote Inclusion and Diversity, and we welcome applicants from diverse backgrounds without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.,

Responsibilities: * Collaborate with team on project planning & execution. * Maintain equipment cleanliness & safety standards. * Load & unload materials onto machine. * Follow quality control procedures during operations. * HBM Operator Annual bonus Provident fund Health insurance

As an HBM, HMC operator, and CNC turner, you will be responsible for operating and maintaining various machines such as Horizontal Boring Mills (HBM), Horizontal Machining Centers (HMC), and Computer Numerical Control (CNC) turning machines. You will play a crucial role in ensuring the efficient and accurate production of components according to specifications. The ideal candidate should have at least 1 year of total work experience in a similar role, although this is preferred and not mandatory. You will be expected to work full-time at the designated work location, where your skills and expertise will be utilized to contribute to the overall manufacturing process. Your responsibilities will include setting up machines, selecting appropriate tools, loading materials, and monitoring the machining process to ensure the quality of the finished products. Additionally, you may be required to make adjustments to machine settings, troubleshoot issues, and perform routine maintenance tasks to keep the equipment in optimal working condition. Overall, this role requires a detail-oriented individual with a strong mechanical aptitude and a good understanding of machining processes. If you are passionate about precision engineering and enjoy working in a dynamic manufacturing environment, this position offers an exciting opportunity to showcase your skills and grow in your career as an HBM, HMC operator, and CNC turner.,

As a member of the Validation team at Micron Technology, you will play a crucial role in the preparation and validation of silicon designs. Your responsibilities will include engaging in pre-silicon activities, collaborating on validation plans, and debugging issues post-silicon arrival. You will be tasked with resolving all silicon findings within designated timelines and fostering partnerships with various teams to ensure effective product delivery. To excel in this role, you should hold a Bachelor's or Master's Degree in Electrical or Computer Engineering and possess at least 8 years of relevant technical experience. Strong circuit analysis and debug skills are essential, with familiarity in HBM and DRAM being preferred. Your ability to identify continuous improvement opportunities and implement lessons learned will be key to success. Additionally, you should demonstrate problem-solving capabilities, excellent communication skills, and a track record of collaboration and performance excellence. Micron Technology is a global leader in memory and storage solutions, driving the transformation of information into intelligence. With a focus on customer satisfaction, technology innovation, and operational excellence, Micron offers high-performance DRAM, NAND, and NOR memory products under its Micron and Crucial brands. By leveraging our innovations, we empower advancements in AI, 5G applications, and data economy, impacting various sectors from data centers to mobile experiences. If you are looking to be part of a dynamic team that shapes the future of technology and data usage, Micron Technology offers a rewarding career opportunity. Visit micron.com/careers to explore our current openings and discover how you can contribute to our vision of enriching life through information. For any inquiries regarding the application process or accommodations, please reach out to hrsupport_india@micron.com. Micron Technology upholds a commitment to ethical practices, prohibiting the use of child labor and complying with all relevant labor laws and standards. Join us in our mission to drive innovation and make a positive impact on the world through transformative memory and storage solutions.,

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

As a Verification Tech Lead at AIsemiCon located in Bengaluru, you will play a crucial role in ensuring the quality and performance of the next-generation products. Your primary responsibility will involve leading a team of verification engineers to execute complex verification strategies for high-performance silicon and system-on-chip (SoC) designs. Your expertise in verification methodologies such as UVM, along with your leadership skills, will be essential in mentoring the team, creating efficient verification plans, and ensuring designs meet the highest quality standards before tape-out. Collaborating closely with architecture, design, and validation teams, you will guarantee thorough verification of chip functionality, performance, and reliability. Your key responsibilities will include defining and driving comprehensive verification strategies, establishing efficient verification methodologies, providing technical leadership to the team, and overseeing the execution of verification tasks. You will also contribute to continuous process improvements by utilizing cutting-edge verification tools and methodologies. Leading, mentoring, and growing a team of verification engineers will be a crucial aspect of your role, fostering a culture of technical excellence and innovation. You will promote continuous learning within the team, conduct design and verification reviews, and provide career development support. Additionally, you will collaborate with various engineering teams to ensure seamless integration of verification and design flows, communicate verification status to senior management, and support post-silicon validation efforts. Your qualifications should include a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, with at least 12+ years of hands-on verification experience and 3+ years in a leadership role. Proficiency in tools like UVM, SystemVerilog, VCS, and ModelSim, along with experience in verification planning, testbench development, and coverage-driven verification, will be crucial for success in this role. AIsemiCon offers a competitive salary, comprehensive benefits package, and a dynamic work environment focused on growth and innovation. If you are an experienced verification professional looking to work on cutting-edge semiconductor technologies and drive successful verification efforts for complex designs, we encourage you to apply by submitting your resume and cover letter to hiring@aisemicon.in with the subject line "Verification Tech Lead".,

You are looking for Analog Mixed Signal Designers to join our team and work on designing building blocks for high-speed IPs such as DDR, LPDDR, HBM, UCIe, and PCIe. As a member of our team, your responsibilities will include deriving circuit block level specifications from top-level specifications, designing optimized transistor-level analog and custom digital blocks, conducting Spice simulations to meet detailed specifications, guiding layout design for optimal performance, matching, and power delivery, performing performance characterization of designs in various conditions including reliability checks, and generating/delivering behavioral, timing, and physical models of circuits. You will also be involved in conducting design reviews at different phases of the design process. To be successful in this role, you should have a BE/M-Tech degree in Electrical & Electronics, strong fundamentals in RLC circuits, CMOS devices, digital design building blocks, and prior experience with custom design environments and spice simulators. A collaborative and positive attitude is essential for working effectively in our team. Depending on your experience level, you will be designated as a Design Team Member (0-4 years), a Technical Lead/Mentor (4-7 years), or a Team Lead/Manager (7+ years). Some example designs you may work on include Wireline channel transmitters, receivers, equalization circuits, serializers, deserializers, bandgap references, PLLs, DLLs, phase interpolators, comparators, DACs, and ADCs. Joining our team will provide you with opportunities for growth and learning, including close collaboration with experienced mentors and exposure to advanced process technologies such as 12nm, 7nm, 5nm, 3nm, and 2nm. We offer a fast-paced environment for high-performance individuals who are ready to take on challenges and advance their careers. If you are interested in this fantastic opportunity, please reach out to poojakarve@arf-design.com to learn more.,

At Cadence, we are seeking individuals who are passionate about technology and aspire to lead and innovate in the field. As a design and verification engineer, you will play a crucial role in making a significant impact on the world of technology. The ideal candidate should hold a BE/BTech/ME/MTech degree in Electrical, Electronics, or VLSI with a minimum of 8 years of experience in Design Verification, specifically with SV/UVM. A strong foundation in functional verification fundamentals, including environment planning, test plan generation, and environment development, is essential for this role. In this position, you will be responsible for verifying complex designs and leading projects from concept to verification closure. Proficiency in UVM and System Verilog coding, as well as experience in functional verification environment development, are key requirements for this role. Additionally, prior experience in IP verification of memory IP such as DDR, HBM, or GDDR would be considered a valuable asset. Join us at Cadence, where we are committed to tackling challenges that others may find insurmountable. Your contributions will be instrumental in solving problems that truly matter in the realm of technology.,

Rivos is on a mission to build the best enterprise SOCs in the world with class-leading performance, power, security, and RAS features. We are seeking Memory Controller design verification engineers to join our team in building the best high-performance memory interface in the world. As a memory subsystem design verification engineer, you'll be responsible for all aspects of digital verification such as functional, performance, DFD, and DFT features around DDR and HBM memory subsystem designs. Responsibilities - Work closely with architect and design team to verify the feature sets of the DDR and HBM memory subsystem design. - Collaborate with 3rd party IP vendors to validate the correctness of integration and custom features. - Develop test plan and testbench. - Integrate and bring up VIPs such as DDR_PHY, DDR_Model as part of the testbench. - Create test stimulus, checkers, and scoreboard in SystemVerilog/UVM. - Conduct debugging, regression testing, and coverage closure. - Provide debug support to emulation and silicon-bring up teams. - Capable of working effectively with teams across different continents. Key Qualifications - Hands-on experience in verifying the digital logic portion of DDR/HBM memory subsystem design. - Familiarity with JEDEC specifications of LPDDRx/DDRx/HBMx. - Understanding of the DDR DFI specification and protocol. - Knowledge of Reliability, availability, and serviceability (RAS) features in the context of memory subsystem, including error detection/correction and encryption. Education And Experience - Masters Degree or Bachelors Degree with 3-5 years of experience.,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Lead Verification Engineer THE ROLE: Candidate should have worked on complex design with hands on experience in developing testbench, UVC, test-planning and execute test plan, coverage development and closure. Candidate actively involve in technical discussion and test plan review. THE PERSON: Experience requires demonstrated technical expertise in functional verification of complex designs including: test planning, test bench development, stimulus generation, checking, and functional coverage. Experience or exposure to Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement Experience or exposure to UVM/OVM is a must. Must demonstrate strong Object Oriented programing skills and concepts. Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is a plus Requires strong communication skills and the ability to work independently as well as in a cross-site team environment. KEY RESPONSIBILITIES: Work with all stakeholders such as design architect and block designer to understand features to be verified. Follow the process and good practices to develop UVC and testbench for design verification. PREFERRED EXPERIENCE: Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is added advantage ASIC design verification experience with 7+Years Hands on experience in developing complex UVC Good debugging skill and good knowledge of verification tool and methodology Hands on experience with coverage planning, coding, and coverage closure Should have worked on developing testplan at module level/IP level /Chip-level project Mentoring Juniors and ensuring that the team achieves technical goals with high quality. ACADEMIC CREDENTIALS: B.E/B.Tech in ECE, Electrical engineering degree or Master's degree preferred with emphasis in Electrical/Electronics Engineering. Preferred VLSI major in post-graduation #LI-SR5 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Wipro Limited is a leading technology services and consulting company dedicated to developing innovative solutions that cater to the most intricate digital transformation needs of clients. With a vast portfolio of capabilities in consulting, design, engineering, and operations, Wipro assists clients in achieving their most ambitious goals and establishing future-ready, sustainable businesses. The company, with over 230,000 employees and business partners operating in 65 countries, is committed to aiding customers, colleagues, and communities in thriving amidst a constantly changing world. For more information, visit www.wipro.com. As a Lead Design Verification Engineer with at least 7 years of hands-on DV experience in SystemVerilog/UVM, you will be responsible for owning and driving the verification of a block/subsystem or a SOC. An ideal candidate should have a proven track record of leading a team of engineers and possess extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Proficiency in Tesplan and Testbench development, execution of test plans using high-quality constrained random UVM tests to achieve coverage goals on time, and adeptness in debugging and exposure to all aspects of verification flow including Gatesims are essential. The candidate must have extensive experience in the verification of technologies such as PCI Express or UCIe, CXL or NVMe, AXI, ACE or CHI, Ethernet, RoCE or RDMA, DDR or LPDDR or HBM, ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages, and Power Aware Simulations using UPF. Experience in using EDA tools like VCS, Verdi, Cadence Xcelium, Simvision, Jasper, and revision control systems such as Git, Perforce, Clearcase is required. Experience in SVA and formal verification is desirable, and knowledge of script development using Python, Perl, or TCL is an added advantage. The position is available in various locations including Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, and Pune. The ideal candidate must have a minimum of 7 years of YoE. Key Responsibilities: - Define product requirements and implement VLSI and hardware devices - Continuously upgrade and update design tools and frameworks - Analyze and select the right components and hardware elements for product engineering - Conduct cost-benefit analysis to choose the best design - Develop architectural designs for new and existing products - Implement derived solutions and troubleshoot critical problems - Evangelize architecture to project and customer teams to achieve the final solution - Monitor product solution and make continuous improvements - Understand market-driven business needs and technology trends to define architecture requirements and strategy - Develop Proof of Concepts (POCs) to demonstrate product feasibility - Provide solutioning for RFPs from clients and ensure overall product design assurance - Collaborate with sales, development, and consulting teams to reconcile solutions to architecture - Provide technical leadership in designing custom solutions using modern technology - Validate solutions from technology, cost structure, and customer differentiation perspectives - Identify and resolve problem areas in architectural design and solutions - Monitor industry and application trends and provide strategic input during product deployment - Support delivery team in product deployment and issue resolution - Develop product validation and performance testing plan in alignment with business requirements - Maintain product roadmap and provide inputs for product upgrades based on market needs - Build competencies and branding through necessary trainings, certifications, and Thought leadership content development - Mentor developers, designers, and junior architects for career enhancement - Contribute to the architecture practice by conducting selection interviews Performance Parameters: - Product design, engineering, and implementation: Measure based on CSAT, quality of design/architecture, FTR, delivery as per cost, quality, and timeline, POC review and standards - Capability development: Measure based on % of trainings and certifications completed, mentorship of technical teams, and development of Thought leadership content Wipro is dedicated to reinventing your world by building a modern, end-to-end digital transformation partner with ambitious goals. The company is looking for individuals who are inspired by reinvention and are committed to constant evolution in their careers and skills. Join Wipro to realize your ambitions and be part of a purpose-driven business that empowers you to design your own reinvention. Applications from people with disabilities are explicitly welcome.,

As a DDR Subsystem Architect at Arm, you will be responsible for designing the hardware architecture of LPDDR, DDR, HBM, and GDDR subsystems for cutting-edge SoC platforms across various market segments including mobile, automotive, datacenter, networking, and IoT. Your role will involve collaborating with SoC architects, business units, and customers to define DDR subsystem features and requirements, authoring architectural specifications, and working with IP vendors to ensure successful execution. You will utilize your deep understanding of DDR controller design, memory types, controller-to-PHY interface protocols, Arm bus protocols, and various features related to DDR subsystems. Your expertise will be crucial in debugging performance and functional issues, drafting design specifications, and supporting execution teams throughout the development process. Additionally, you will be expected to leverage your excellent communication skills to effectively collaborate with cross-functional teams. To excel in this role, you should possess a Bachelor's or Master's degree in Electrical or Computer Engineering along with a minimum of 10 years of experience in a senior development position. Your ability to work strategically, think innovatively, and contribute actively to ongoing projects will be key to your success in this dynamic and fast-paced environment. Joining the Solutions Engineering SoC architecture team at Arm will provide you with significant opportunities to shape the team's culture and drive future success. Arm values collaboration, creativity, innovation, personal development, and impact, and as a team member, you will be encouraged to embody these core behaviors in your work. As an integral part of the Arm team, you can expect a competitive salary range of $253,300-$342,700 per year, along with a total reward package that reflects the company's commitment to recognizing and rewarding individual contributions. Arm is dedicated to building extraordinary teams, and if you require any accommodations during the recruitment process, you can reach out to accommodations@arm.com for assistance. Arm's hybrid working approach is designed to support high performance and personal wellbeing, allowing teams to determine their own working patterns based on project requirements and personal needs. The company is committed to providing flexibility while adhering to local regulations, and adjustments can be made to accommodate individual circumstances. Arm promotes equal opportunities and is committed to fostering a diverse and inclusive work environment for all employees.,

As a Senior Analog Circuit Design Engineer at Eximietas Design, you will be responsible for demonstrating a strong understanding of Analog & Mixed Signal Design fundamentals. Your primary focus will include the design implementation of SERDES blocks such as Transmitter, CTLE, SAL, DLL, Phase Interpolator, DFE, and FFE, as well as Bandgap references and voltage monitors. In this role, you will leverage your expertise in Die to Die interconnect high-speed IO designs, HBM, DDR, and UCIe protocols. Hands-on experience with lower FINFET technology nodes and a solid grasp of basic analog layout knowledge, particularly in relation to FINFET technology, will be key to your success. You will be expected to be proficient in utilizing tools such as Cadence and Synopsys mixed signal design tool flow, adhering to industry standards while working on various projects. The ideal candidate for this position should possess a minimum of 4+ years of experience in Analog circuit design and have the ability to work autonomously. This position is based in Visakhapatnam, Bangalore & Ahmedabad. If you are a passionate Engineer with the requisite skills and experience, we encourage you to share your updated resume with us at maruthiprasad.e@eximietas.design. We look forward to potentially welcoming you to our team at Eximietas Design.,

We are looking for experienced Senior/Lead ASIC Verification Engineers for our Noida-VIP team. Does this sound like a good role for you Experience : 5yrs to 15 years (multiple roles) Location: Noida Associated with Verification especially using industry-standard protocols & methodology Languages: Hands-on experience with System Verilog & Verilog . Should have a good understanding of Object Oriented Programming. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies . Protocol experience: Should have experience on any of the UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective Please share your updated CV to [HIDDEN TEXT] or refer who would like to explore this opportunity. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Show more Show less

Responsibilities: * Ensure quality control during production processes * Maintain machinery and report issues promptly * Follow safety protocols at all times * Load, operate & unload boring machines according to specifications Food allowance Provident fund

Responsible for planning, executing, monitoring & improving CNC/VMC machining operations, Machine Shop production & overall performance in shifts Ensure all are properly set up, operated,and maintained for maximum efficiency. Ensure machine setup Required Candidate profile manage the daily operations of CNC machines, ensuring all setups, operations, and quality checks, CNC programming, setting. Supervise, train, and support machine operators, .

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

You will play a crucial role in developing Interface and Analog IPs for internal ASIC or external customers. This will involve hands-on experience with Hard Analog or PHY blocks on circuit design using the latest finfet nodes like 16nm and 7nm. Your responsibilities will include driving processes to establish a solid IP Development methodology for successful outcomes with customers. Additionally, you should be able to provide support for multiple customers and IP Deliveries, possessing strong knowledge in all aspects of IP integration such as logic design and verification, physical design, packaging, test, and characterization. To excel in this role, you should have a minimum of 6 years of experience in IP Design and delivery of complex analog, mixed signal IPs or PHYs. Previous exposure to DDR, HBM, and SerDes is highly preferred. A Masters Degree or equivalent in Electronics and Computer Engineering is the minimum educational qualification required, with a preference for a PhD. Expertise in the complete ASIC and IP development life cycle is essential, along with a desire for hands-on engineering experience throughout the ASIC/IP development flow. Excellent verbal and written communication skills are crucial, including the ability to engage effectively with customers and vendors. As part of our commitment to employee well-being and satisfaction, we offer a comprehensive benefits package that includes competitive compensation, Restricted Stock Units (RSUs), opportunities for advanced education from Premium Institutes and eLearning content providers, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snacks facility. At Alphawave Semi, we prioritize Diversity & Inclusivity. We are an equal opportunity employer and encourage applications from all qualified individuals, including visible minorities, Indigenous People, and persons with disabilities. If you require accommodation as a qualified job applicant, we will work with you to provide reasonable accommodations tailored to your specific needs. If your application is selected to proceed in our hiring process, you will have the opportunity to request accommodations.,

You will be joining Eximietas as a Senior Design Verification Engineer/Lead in Bengaluru with 5-15 years of experience. Your primary responsibility will be to lead the SoC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. This includes developing and implementing comprehensive verification strategies for high-speed and low-speed peripherals such as I2C, SPI, UART, GPIO, QSPI, as well as high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR, HBM. You will be conducting Gate-level simulations and power-aware verification using tools like Xprop and UPF. Collaboration with cross-functional teams, including architects, designers, and pre/post-silicon verification teams, will be crucial to ensure alignment and seamless integration of verification efforts. Your role will involve analyzing and implementing System Verilog assertions and functional coverage to ensure thorough verification of design functionality. Mentorship and technical guidance to junior verification engineers will be part of your responsibilities to elevate team performance. Leading and managing a dynamic team of verification engineers, fostering a collaborative and innovative work environment will be essential. You will also ensure that all verification signoff criteria are met, with clear and comprehensive documentation. Your dedication, work ethic, and commitment to meeting project goals and deadlines will be vital. Upholding quality standards and implementing best test practices to contribute to continuous improvements in verification methodologies will also be expected. You will work with verification tools from Synopsys and Cadence, including VCS and Xsim, and integrate third-party VIPs (Verification IP) to enhance verification coverage. To qualify for this role, you should have 5+ years of hands-on experience in SoC Design Verification and expertise in verification of high-speed SoCs and various protocols. Proficiency in System Verilog for verification, gate-level simulations, and power-aware verification using Xprop and UPF are necessary. Strong hands-on experience with VCS and Xsim from Synopsys and Cadence, mentorship experience, and demonstrated ability to work with cross-functional teams are also required. A strong understanding of verification methodologies and the ability to contribute to their continuous improvement are essential.,

As a Principal Software Engineer at Cadence, you will have the opportunity to work on cutting-edge technology in an environment that encourages creativity, innovation, and making a real impact. Cadence, a pivotal leader in electronic design, with over 30 years of computational software expertise, is seeking a candidate to join their highly talented team in Bangalore or Ahmedabad. In this role, you will be responsible for developing, implementing, and testing features for the next generation of verification IP tools. The ideal candidate should have excellent communication skills, the ability to quickly ramp up on new technologies independently, and a strong background in functional verification using SV/UVM. Additionally, hands-on knowledge of Python/Scripting, experience with memories such as HBM, LPDDRR, GDDR, and DDR, as well as prior VIP usage and development experience would be advantageous. Cadence offers an employee-friendly work environment that focuses on the physical and mental well-being of its employees, career development, learning opportunities, and celebrating success. The company's unique One Cadence - One Team culture promotes collaboration to ensure customer success, while providing avenues for learning and development based on individual interests and requirements. Qualifications for this role include a BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent, along with strong analytical and communication skills. The successful candidate should be self-motivated, possess strong written, verbal, and presentation skills, and have the ability to establish close working relationships with both customers and management. Creativity, the willingness to explore unconventional solutions, and the ability to work effectively across functions and geographies are essential behavioral skills required for this position. Join Cadence and be part of a diverse team of passionate individuals dedicated to making a difference in the world of technology. If you are ready to work in a supportive and friendly environment where innovation and collaboration are valued, we encourage you to apply for the Principal Software Engineer position by sending your CV to kmadhup@cadence.com. Regards, Madhu,

Must know how and experience of different types of CNC machines like HMC, VMC, turning center, VTL, Horizontal Boring Machine, Vertical Turning Center and Turn-mills. Hands-on experience of Heavy parts Machining

Must know how and experience of different types of CNC machines like HMC, VMC, turning center, VTL, Horizontal Boring Machine, Vertical Turning Center and Turn-mills. Hands-on experience of Heavy parts Machining

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

designations : Deburring technicians experiences : 1 to 10 yrs salary : 15 k to 35 k locations : Chennai -Irungattukottai job descriptions : have experiences in HBM , VTL ,Deburring technicians contact us or WhatsApp 7550079132

Good setting and programming knowledge in VMC,HMC & HBM Makino & Doosan machine Well experience knowledge in programming Benefits : Accommodation free of cost ,Food 50% subsidy For 3 Times, Double OT, Esi,Pf,Bonus,Gratuity,Etc. PMAC.PVT.LTD Email id: hr@pmacindia.com Role & responsibilities