7 Xcelium Jobs

Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Job Description In your new role you will: Candidate should have working experience with AMS Verification on multiple SOCs or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Your Profile You are best equipped for this task if you have: Bachelors with 5+ years or Masters with 4+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently Contact: [HIDDEN TEXT] #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

8+ yrs of experience in AMS verification and mixed-signal design, UVM System Verilog (UVM/SV), and C-based compile flow, ARM M-series (Cortex M33, M85, M55, M4, M0 etc) and RISC-V processor, Spectre and Xcelium tools, scripting - Python, Perl

Job Specs : We are seeking a highly skilled and motivated ASIC Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore, Pune. Malaysia, Singapore Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering Visa / work permit sponsored for immediate hires Expertise in ASIC SOC verification Expertise in PCie Expertise in UVM, System Verilog and constrained random testing. Expertise in testbench architecture and SOC-level verification strategies. Expertise with protocols such as AXI, AHB, APB, USB, or DDR. Expertise with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa. Familiar with waveform debugging tools such as Verdi or DVE. Working knowledge of low-power verification (UPF) and DFT / scan concepts. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Job Specs : Develop and maintain full-chip verification environments using SystemVerilog UVM methodology. Define and execute test plans for SoC-level functionality, power intent (UPF), coherency, performance and interconnect protocols (e.g., AXI/ACE). Work closely with the RTL, DV, and integration teams to ensure complete coverage of functional and architectural features. Implement and manage stimulus generators, scoreboards, monitors, and checkers at full-chip level. Perform debugging, waveform analysis, and triage of failures in RTL simulations. Ensure code coverage and functional coverage goals are met and signoff criteria are satisfied. Collaborate with firmware/software and post-silicon teams to align verification efforts and resolve issues. Participate in formal verification, assertion-based verification, and low-power simulations. Support regression testing, issue tracking, and coverage closure. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We are seeking a results-oriented Senior Digital Verification engineer to join our team focusing on development of the next generation of ADI s Gigabit Multimedia Serial Link products delivering best-in-class solutions for in-car infotainment and advanced driver-assistance systems (ADAS). A small amount of travel is expected. The position offers opportunities for development. JobResponsibilities: Verification of complex ASIC chips and sub-systems using leading edge verification methodologies Define test plans, tests and verification methodology for block and chip level verification. Employ UVM/SystemVerilog based verification methodologies and use scoreboard, assertions, functional/code coverage, formal verification etc to reach verification goals. Take complete ownership for a complex feature verification and technically mentor & guide junior verification engineers. Define and implement improvements in verification flow and methodology. Gate level simulations and debug of large digital blocks and full-chip ASICs Support post-silicon validation activities of the products working with design, applications and test team. Job Requirements: Bachelors or masters degree in Electrical or Computer Engineering with 7+ years of experience in digital verification. Expertise in Verilog, System Verilog, UVM, object-oriented programming, scripting and automation with Perl or Python. Firm understanding of constrained random functional verification, coverage, and assertions. Expertise in test plan development and development of verification environments from ground up. Extensive experience with verification of complex blocks, regressions and coverage closure. Experience with gate level simulations and debug. Excellent debugging, analytical and problem-solving skills. Strong inter-personal, teamwork and communication skills. Expected to be highly independent, proactive and result-oriented to achieve verification goals. Preferred qualifications: Knowledge of Video (DisplayPort, CSI/DSI), PCIe, Ethernet, I2C, UART, SPI and Audio I2S protocols.. Experience with lab silicon bring-up, validation and production test support. Experience in technically mentoring, coaching junior engineers.

Hands-On UVM at user level, pseudo and constrained random techniques, assertion-based verification techniques with System Verilog. Verification of analog interface is a value add along with ARM based subsystem, core sight, security subsystem verification exposure. 3rd party, industry-standard simulator productivity improvements and breakthrough innovations, integration into ADI DV solutions and creating differentiating solutions Evaluate, utilize existing and develop new verification infrastructure frameworks, tools, and methodologies to enhance the verification process for efficiency and quality Job Requirements: BTech/MTech degree in Electrical/Electronics/VLSI with 3-6 years of experience from reputed institutes Strong hands-on experience in Cadence/Synopsys simulation and debug tools like Xcelium/VCS, vManager, Verisium, Verdi or similar is required Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer. Coding up in C tests on M3 Series Cortex based products. Expertise in automation and scripting languages like Perl, Python, and shell scripting Proficient in Version control systems, such as Perforce, SVN, SOS Proficient in Verilog, System Verilog and UVM Ability to manage multiple tasks and work effectively in a fast-paced environment Able to communicate effectively Good debugging and analytical skills

Job Specs : We are seeking a highly skilled and motivated ASIC SOC & GLS Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Remote, Work From Anywhere Work Expertise: 7 Years 10 Years Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. Expertise in ASIC SOC verification. Expertise in UVM, System Verilog and constrained random testing. Expertise in Gate Level Simulation tools (GLS) or verification related to display port or memory controller Expertise in testbench architecture and SOC-level verification strategies. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Preferred immediate hires only Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

GLS Verification Create or modify testbenches compatible with gate-level netlists. Set up timing annotations using SDF (Standard Delay Format) files. Configure simulation tools (like VCS, ModelSim, or Xcelium) for GLS.