28 Xcelium Jobs

You will be responsible for developing and executing AMS verification plans for mixed-signal IP and SoCs. This will involve creating and validating behavioral models using Verilog-A for analog and mixed-signal blocks. You will also implement and optimize AMS testbenches in the Xcelium simulation environment. Collaboration with analog and digital designers to verify top-level integration and system performance will be a key aspect of your role. In addition, you will be expected to debug and resolve complex AMS simulation and modeling issues. Your contribution to the development of AMS verification methodologies and best practices is crucial. Regression testing and coverage analysis must be pe...

As a Functional Verification Engineer, you will be responsible for verifying RTL designs using SystemVerilog and UVM. Your role involves developing testbenches, building reusable components, and ensuring complete functional coverage of IPs or SoC-level designs. Key Responsibilities: - Develop and maintain UVM-based testbenches for IP/subsystem/SoC verification - Create test plans from microarchitecture/design specifications - Write and debug directed and constrained-random tests - Implement functional coverage, assertions (SVA), and checkers - Run regressions using simulators like VCS, Xcelium, or Questa - Interface with RTL, DFT, and Firmware teams to track and resolve bugs - Analyze wavefo...

As a semiconductor company, ST believes in the power of technology to drive innovation and make a positive impact on people, business, and society. You will be part of a global business of diverse creators and makers from over 115 nationalities, dedicated to pushing boundaries and driving innovation around the world. Join ST to unlock your potential and be a part of shaping the future with cutting-edge technology. **Role Overview:** As part of the verification team, your main responsibility will be to drive towards zero-defect by developing verification test benches, verification components, and test cases for simulation. You will also be involved in debugging failures and creating simulatio...

About Iravan Iravan Technologies, headquartered in Pune, is a semiconductor design services company specializing in Mixed-Signal, Digital, and Formal Verification. We partner with leading companies across Storage, Networking, Aerospace, Automotive, Defense, and other critical industries to deliver advanced semiconductor solutions. Role Expectations (JD): Hands-on experience in designing Analog IPs such as LDOs, Bandgaps, ADCs, DACs, and Bias Circuits across various technology nodes. End-to-end ownership from specification to silicon including design, simulation, verification, and layout support. Strong understanding of analog fundamentals, circuit behavior, and CMOS process variations. Profi...

Job Description: Were looking for a talented GLS (Gate-Level Simulation) Verification Engineer with strong experience in verifying complex SoCs using industry-standard tools and methodologies. Key Responsibilities & Skills: * Hands-on experience in GLS verification using Cadence Xcelium (mandatory) and Synopsys VCS. * Minimum 3 years of GLS experience with a solid understanding of gate-level verification flows. * Good understanding of physical design concepts relevant to GLS verification. * Strong knowledge of SystemVerilog and UVM-based testbench environments. * Experience with DDR or HBM PHY GLS will be an added advantage. * Basic understanding of SoC design and common bus protocols (AMBA,...

Grow with us About this Opportunity: Are you passionate about driving innovation and working on groundbreaking 5G and 6G mobile communication solutions Do you thrive in a flexible working culture, where new insights are championed, and you are encouraged to develop new skills We are looking for an FPGA Verifier to join the Ericsson Silicon organization. You will work with dedicated engineers who are passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA teamdefining verification strategies and implementing environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, you'll col...

In your new role you will: 10+ years of Digital Verification experience and a deep understanding of all technical aspects of Verification, including 2+years of technical leadership activities Masters/bachelor's in electrical/Electronic Engineering or ComputerScience. Familiarity with version-controlling (eg, Git/Bitbucket, ClearCase,CVS, SVN) and bug-management systems (eg, JIRA). Good to have: Knowledge of ISO26262 and ISO21434. Outstanding Expertise in digital verification and all tasks needed to achieve design verification closure, including state of the art tools and methodologies (SV-UVM, Xcelium, vManager, Certitude, etc) Verification experience in Graphics IP design, cryptographic har...

Candidate should have working experience with AMS Verification on multiple SOC's or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched ...

Candidate should have working experience with AMS Verification on multiple SOC's or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched ...

Hiring DFT Lead (10–20 yrs) with expertise in ATPG, Scan/MBIST/JTAG, pattern validation, Synopsys/Cadence/Mentor tools, Perl/TCL scripting, and strong leadership skills. Required Candidate profile Experienced DFT Lead (10–20 yrs) skilled in ATPG, Scan/MBIST/JTAG, pattern validation, Synopsys/Cadence/Mentor tools, Perl/TCL scripting, debugging, and leadership.

You will be working as an AMS Verification Engineer with a focus on Analog-Mixed Signal designs. Your role will involve developing and executing verification plans, performing behavioral modeling, and ensuring the functionality and performance of various AMS circuits like PLLs, ADCs, DACs, and LDOs. - Develop AMS verification plans based on design specifications. - Perform mixed-signal co-simulation using tools such as Cadence Virtuoso, Spectre, and Xcelium. - Create Verilog-A/Verilog-AMS behavioral models for analog/mixed-signal blocks. - Develop testbenches using UVM-AMS or other methodologies for mixed-signal verification. - Define and execute functional, performance, and corner case veri...

The DFT Engineer will focus on developing and implementing Design for Test strategies and techniques to test the complex IoT products which has WIFI & Blue tooth combo devices. He will work closely with design and backend, verification teams to ensure robust testing mechanisms and improve overall product quality and reliability. Job Description In your new role you will: Develop and implement Design for Test (DFT) methodologies for IoT products. Collaborate with design and backend teams to integrate DFT features. Create and validate test plans to ensure thorough coverage and fault detection. Support silicon bring-up and debug activities. Automate test processes such as ATPG/MBIST to enhance ...

About Iravan Iravan Technologies, headquartered in Pune, is a semiconductor design services company specializing in Mixed-Signal, Digital, and Formal Verification. We partner with leading companies across Storage, Networking, Aerospace, Automotive, Defense, and other critical industries to deliver advanced semiconductor solutions. Designation : AMS Verification Engineer Experience: M.Tech + 1 year of relevant industry experience in Analog Domain OR 2+ years of experience in AMS Verification Location: BLR/Pune/HYD Vacancies :03 JD Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks Writing and maintaining Analog Mixed Signal models, using ...

DV Engineer Experience : 1-3 years Location : Hyderabad Verilog, System verilog, UVM VHDL, UVVM 3rd party simulator exposure with VCS, Questa, Xcelium Proficient in simulation and HW languages Should be able to interpret various LRMs and comply with semantics and testcase creation. Interested,please drop your updated resume to [HIDDEN TEXT]

Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Job Description In your new role you will: Candidate should have working experience with AMS Verification on multiple SOC's or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral ...

Key Responsibilities: Develop and execute verification test plans based on design specifications. Create constrained-random and directed testbenches using SystemVerilog/UVM. Develop functional coverage models and drive coverage closure. Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues. Perform block-level and/or SoC-level verification. Integrate and verify 3rd-party IPs and custom IPs in subsystem and full-chip environments. Collaborate with RTL, DFT, DV, firmware, and physical design teams. Run regression simulations and ensure verification quality through coverage metrics. Automate verification flows and improve efficiency using scripting language...

Job Overview: We are seeking a highly skilled and motivated Design Verification Lead to join our advanced VLSI design team. The ideal candidate will have strong expertise in SystemVerilog, UVM (Universal Verification Methodology), and verification of industry-standard protocols (e.g., PCIe, USB, Ethernet, DDR, etc.). As the Design Verification Lead, you will lead the verification of complex SoC and IP designs, mentor verification engineers, and collaborate closely with design, architecture, and validation teams to deliver high-quality, robust products. Key Responsibilities: Lead the design verification efforts for complex SoC/IP projects following best practices. Develop and maintain verific...

Drive innovation, process improvements, and mentor engineers, drivingdigital verification and post-silicon validation as a technical lead. Job Description In your new role you will: Lead the digital verification of complex digital design Ips andSubsystems, ASIC and SoCs. Coordinate the overall digital verification activities such asverification planning, verification tracking and reporting, as well asrequirement-based verification Collaborate with cross-functional teams, including concept, design toensure high quality designs Hands-on contributor to digital verification either from scratch, orusing legacy verification environments and flows Focus on reuse of the Verification Components to be...

You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NC...

Lead Design Verification Engineer Bangalore We are looking for an experienced Lead Design Verification Engineer (412 yrs) to join our semiconductor team. Youll lead SoC/ASIC/IP verification using SystemVerilog, UVM, SVA, and drive test planning, coverage, regressions, and debug. ???? Must-have: Strong expertise in protocols (PCIe, DDR, USB, AMBA, MIPI, CXL), EDA tools (VCS, Xcelium, Questa), scripting (Python/Perl/Tcl), and low-power/CDC/formal verification. ???? Bonus: Experience with emulation/GLS, lint, DFT awareness, and leadership/mentoring. ???? Location: Bangalore, India ? Experience: 412 years ???? Apply now or share your profile at [HIDDEN TEXT] Show more Show less

Build your career with Sykatiya Technologies, a company that values Technical Ability and the Attitude of its highly talented team. Our team consists of skilled engineers and experts from various domains such as Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently looking for candidates for the role of RTL/ IP Design with 3-12 years of experience to join our team in Bangalore. As an ideal candidate, you should have at least 5 years of experience in digital ASIC front-end design. You should possess a thorough understanding of design flows including RTL (VHDL, Verilog, and/or SystemVerilog). Experience with simulation tools like Questa or Xcelium and lo...

Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Job Description In your new role you will: Candidate should have working experience with AMS Verification on multiple SOCs or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral m...

8+ yrs of experience in AMS verification and mixed-signal design, UVM System Verilog (UVM/SV), and C-based compile flow, ARM M-series (Cortex M33, M85, M55, M4, M0 etc) and RISC-V processor, Spectre and Xcelium tools, scripting - Python, Perl

Job Specs : We are seeking a highly skilled and motivated ASIC Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore, Pune. Malaysia, Singapore Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering Visa / w...

We are seeking a results-oriented Senior Digital Verification engineer to join our team focusing on development of the next generation of ADI s Gigabit Multimedia Serial Link products delivering best-in-class solutions for in-car infotainment and advanced driver-assistance systems (ADAS). A small amount of travel is expected. The position offers opportunities for development. JobResponsibilities: Verification of complex ASIC chips and sub-systems using leading edge verification methodologies Define test plans, tests and verification methodology for block and chip level verification. Employ UVM/SystemVerilog based verification methodologies and use scoreboard, assertions, functional/code cove...