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Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Job Description In your new role you will: Candidate should have working experience with AMS Verification on multiple SOCs or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Your Profile You are best equipped for this task if you have: Bachelors with 5+ years or Masters with 4+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently Contact: [HIDDEN TEXT] #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort coming up with alternative verification plans, Mentoring Junior engineer Partial Ability to drive MSV project independently Drive enhancements in known methodologies You are best equipped for this task if you have: Bachelors with 5+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently Contact: [HIDDEN TEXT] #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

You are a skilled SOC Verification engineer with over 3 years of experience in the field. Your expertise includes a strong knowledge of ARM architecture, CPU fundamentals, and Cache coherency. You are proficient in programming languages such as C/C++, assembly, and scripting languages. Additionally, you have a good understanding of low-power design and verification methodologies. In this role, you will be responsible for developing CDV UVM verification environments at the system level. You will verify CPU connectivity to IP blocks and develop SoC test plans and test cases. Tracking metrics, including code and functional coverage, will be an essential part of your responsibilities. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. You must have a minimum of 3 years of experience in SoC ASIC/FPGA verification. Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is required. Experience with simulation, emulation, and formal verification techniques is also necessary. Strong debugging and problem-solving skills will be beneficial in this role. This position is located in Noida, and the ideal candidate should possess a BTECH/MTECH degree in Electrical/Electronics/Computer Science Engineering or an equivalent field.,

HCL Technologies is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. With a strong foundation built on four decades of innovation, a world-renowned management philosophy, and a relentless focus on customer relationships, we pride ourselves on our culture of invention and risk-taking. HCL is committed to diversity, social responsibility, sustainability, and education initiatives, exemplified by our worldwide network of R&D facilities and co-innovation labs. With over 187,000+ Ideapreneurs across 50 countries, we deliver holistic services across industry verticals to leading enterprises, including 250 of the Fortune 500 and 650 of the Global 2000. Enterprises today are at a critical juncture where digital technologies such as analytics, cloud, IoT, and automation are key to success. To help enterprises leverage these technologies for their business objectives, HCL offers an integrated portfolio of products and services through three business units: IT and Business Services (ITBS), Engineering and R&D Services (ERS), and Products and Platforms (P&P). As a Technology Manager at HCL Technologies in Ha Noi or Ho Chi Minh (Vietnam), your responsibilities will include managing technology in projects, providing technical guidance or solutions, developing and guiding team members to enhance their technical capabilities, preparing status reports to minimize exposure and risks on projects, ensuring process compliance, and participating in technical discussions or reviews. **Responsibilities:** - Manage technology in projects and provide technical guidance or solutions - Develop and guide team members to enhance their technical capabilities - Prepare and submit status reports to minimize exposure and risks on projects - Ensure process compliance in the assigned module and participate in technical discussions or reviews **Requirements:** - 5+ years of experience - Bachelors/Masters degree in Electronics/Electrical Engineering with 5+ years of experience in verification - Good understanding of ASIC/SoC life cycle - Experience in OVM/UVM methodologies using SV - Experience with Full chip test plan development/modification - Experience with Testbench development/modification, Test case development, coding, execution, bug analysis, Regressions, coverage analysis, Verification closure - Experience in prevalent standards & Protocols viz. PCIe Gen3/4/5/USB3/DDR4/5, /Ethernet/CSI2/I3C/AMBA - Experience with Gate level simulations - Experience in scripting - Participation in multiple ASIC/SoC verifications till tape out stage - Good command of English. Opportunity to work onsite in Japan **Benefits:** - 18 paid leaves per year (including 12 annual leaves + 6 personal leaves) - Insurance plan based on full salary + 13th salary + Performance Bonus - 100% full salary in probation period - Medical Benefit for Employee and Family - Fast-paced, flexible, and multinational working environment - Opportunity to travel onsite (in 49 countries) - Internal Training (Technical & Functional). Scope of English Training - Working hours: 8:30 AM-6:00 PM, Mondays to Fridays,

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

Description As a Design Verification Manager, you will contribute to exploring innovative hardware designs to enhance our devices You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices You will participate in the bringup of such blocks on Simulation and Emulation platforms, Role You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices In this role, you will: Architect and implement verification environments for complex functional blocks Create and enhance verification environments using SystemVerilog and UVM Develop comprehensive test plans through collaboration with design engineers, SW and architects Implement coverage measures for stimulus and corner-case scenarios Participate in test plan and coverage reviews Drive complex RTL and TB debugs Drive UPF based low power verification Contribute to verification activities across simulation and emulation platforms Work on creating the automation scripts to support DV methodologies Create infrastructure to performs system level performance analysis Manage a team of 6-8 DV Engineers Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent 10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks Managing a team of DV Engineers Experience with RTL development environments Proficiency in hardware description languages and verification methodologies Experience verifying complex IP blocks integrated into SOCs Knowledge of verification platforms including UVM, emulation, and FPGA Demonstrated success in test plan development and verification infrastructure Experience with industry-standard tools and scripting languages (Python or Perl) Understanding of object-oriented programming concepts Preferred Qualifications Advanced degrees in Computer Science, Electrical Engineering, or related field Experience with ARM and DSP instruction set architectures Expertise in system-level debugging Strong programming skills in SV, UVM and C Knowledge of AMBA bus protocols Experience with formal verification methods Experience with Low power verification methods Experience with Baremetal processor environments Transaction level modelling expertise Familiarity with industry standard I/O interfaces FPGA and emulation platform knowledge Understanding of SoC architecture Strong verbal and written communication abilities Our inclusive culture empowers Amazonians to deliver the best results for our customers If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, amazon jobs / content / en / how-we-hire / accommodations for more information If the country/region youre applying in isnt listed, please contact your Recruiting Partner, Company ADCI BLR 14 SEZ Job ID: A3037911 Show

As a Staff Engineer - Design Verification at Micron Technology, you will be part of a highly innovative and motivated design team working on cutting-edge memory technologies to develop advanced DRAM and Emerging memory products. Your role will involve verifying high density memory chips with complex circuit capabilities, ultra-high-speed designs, and next-generation DDR/LPDDR technologies. You will collaborate with various design and verification teams globally to ensure the successful completion of design projects. Your responsibilities will include: - Taking ownership of verification and conducting end-to-end analysis of complex block-level custom designs for DDR4, LPDDR4, DDR5, and LPDDR5 memory architectures operating at high speeds. - Guiding and directing the verification effort for all projects undertaken by the team. - Providing verification support by simulating, analyzing, and debugging pre-silicon block level/full chip designs. - Developing test cases and stimulus to enhance functional coverage for DRAM and emerging memory products. - Creating and maintaining test benches and test vectors using simulation tools, running regressions for coverage analysis, and collaborating with international colleagues to develop new verification flows. - Contributing to the development of verification methodologies and environments for advanced DRAM and emerging memory products. - Demonstrating a good understanding of digital/mixed-signal circuits and experience in digital/mixed-signal verification. - Utilizing tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, and Hspice. - Writing Verilog and Real Number Models, as well as building SV testbenches at block and full-chip levels. - Implementing SV and UVM-based verification, with proficiency in scripting using Perl and Python. - Having previous experience in DRAM memory-related fields is advantageous, along with possessing strong communication, debugging skills, and the ability to work effectively in a team. To qualify for this role, you must hold a Bachelor's or Post Graduate Degree in Electronics Engineering or a related field, with 5-15 years of relevant experience. Micron Technology, Inc. is a global leader in memory and storage solutions, driving innovations that enhance the way information is used to enrich life for all. With a focus on customer satisfaction, technology leadership, and operational excellence, Micron offers a range of high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. The advancements made by Micron's team members contribute to the data economy, enabling progress in artificial intelligence and 5G applications across various platforms. For more information, please visit micron.com/careers. If you require assistance during the application process or need accommodations, please contact hrsupport_in@micron.com. Micron Technology strictly prohibits the use of child labor and complies with all relevant laws, regulations, and international labor standards.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 4 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Must Have: SV/UVM, Test Bench Development , Any Protocols Must be able to own and drive the verification of a block / subsystem or a SOC. Must have extensive experience in verification Share resume to mansoor@hisoltech.com

You will work in the AMS Verification domain, requiring relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is considered a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools is essential. You should have knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles. Analog circuit basics understanding is necessary, and previous analog design experience would be a plus. You should be familiar with the concepts of behavioral modeling, including digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from a mixed signal perspective is advantageous. Functional knowledge of analog and mixed signal building blocks such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Previous experience working on AMS Verification on multiple SOCs or sub-systems is required. Working knowledge of Perl/Skill/Python/Tcl or other scripting relevant languages would be beneficial. You must possess the ability to lead a project team and work collaboratively in a multi-site development environment. Being delivery-oriented, passionate to learn and explore, transparent in communication, and flexible related to project situations is important. A good knowledge of analog and mixed signal electronics, test-plan development, tools, and flows is necessary. You will be responsible for developing and executing top-level test cases, self-checking test benches, and regression suites. Additionally, you will develop and validate high-performance behavior models and verify block-level and chip-level functionality and performance. Being a team player with good communication skills and having previous experience in delivering solutions for a multi-national client is valuable. You should be fluent with Cadence-based flow, creating schematics, Simulator/Netlist options, etc. Ability to extract simulation results, capture them in a document, and present them to the team for peer review is required. Supporting silicon evaluation and comparing measurement results with simulations is part of the role. Having UVM and assertion knowledge would be an advantage.,

Position: Design Verification Engineer Experience: 48 Years We are looking for a skilled Design Verification Engineer with hands-on experience in MIPI protocols and Display IP. For any queries or further details, feel free to reach me at karthik.adasu@Proxilera.com Responsibilities: Experience in MIPI protocol verification (e.g., MIPI DSI, CSI). Strong hands-on experience in Display IP verification and validation. Ability to develop and execute verification plans targeting display and MIPI components. Perform RTL, gate-level, low-power simulations; ensure ISO 26262 compliance. Build SystemVerilog/UVM testbenches tailored to MIPI and Display IPs. Perform simulation and debug activities for MIPI/Display-related RTL modules. Collaborate with RTL and integration teams to resolve display and MIPI interface bugs. Integrate MIPI and Display IPs into subsystem or SoC-level test environments. Implement protocol-specific checkers, monitors, and assertions. Analyze functional coverage metrics related to display pipelines and MIPI interfaces. Work closely with post-silicon and firmware teams to validate MIPI and display functionality

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills Exposure in developing testbench environment, debugging and triaging fails. Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure, lead verification team. Drive complex scenarios, participate in High level design discussions. Track record in leading teams. Preferred technical and professional experience Writing test plans, building random / exhaustive formal verification environment, functional and coverage analysis and debug. Good understanding of the Server System

As a Design Verification Engineer at our Hyderabad location, you will be responsible for verifying the design of industry-leading products, such as Graphics DDR7. With 5-7 years of experience in SV, UVM, Test Bench Development, Soc, Full-chip verification, and memory experience, you will play a crucial role in ensuring the quality and reliability of our products. Your primary responsibilities will include Verilog simulation, UVM methodology implementation, and full-chip verification. Familiarity with memory interfaces is highly preferred. Additionally, you will have the opportunity to work on projects involving GLS, STA, Python knowledge, and circuit characterization. We are looking for someone with a quick learning ability, a positive attitude, and strong technical skills in system Verilog and UVM. Your educational background should include a bachelor's degree, and any experience in static timing analysis, GLS, and Python automation for test bench development will be advantageous. Strong communication skills are essential for this role, as you will be required to effectively convey complex technical concepts to your peers. A proactive learner with strong analytical and problem-solving skills will thrive in this dynamic environment. If you are a local candidate and an immediate joiner with a passion for design verification and a desire to work on cutting-edge products, we would love to hear from you. Join us in our mission to deliver high-quality products to our customers and make a significant impact in the industry.,

The ideal candidate for the position should be a self-motivated and multi-tasker, with a demonstrated ability to work well in a team setting. As part of the team at Centum T&S, you will be responsible for delivering assigned tasks with a focus on quality. Your role will involve interacting with cross-functional teams to resolve any issues that arise. Strong communication skills and leadership qualities are essential as you collaborate with global stakeholders and report to the Project Manager. Your responsibilities will include working on cutting-edge FPGA-based verification environments that encompass System Verilog (SV) and Universal Verification Methodology (UVM). You will need expertise in IP verification, testbench design, and debugging skills. Experience in working on complex test benches and models in UVM-System Verilog is crucial. Additionally, you will be involved in reviewing design changes from a verification complexity perspective, architecting verification IPs and environments, and optimizing verification flows. Analyzing simulation data to identify and resolve issues efficiently, developing and deploying methodologies within the team, and mentoring other team members will be part of your role. Collaboration with other FPGA engineering teams to ensure high-quality verification environments and RTL deliverables will be essential for success in this position. Key values for the role include a results-oriented approach, customer focus, timely delivery of high-quality work, and a positive attitude. Desirable characteristics include trust-building, adaptability to change, continuous learning, proactive behavior, and a joyful disposition. The ideal candidate should have experience in constrained-random verification, architecting functional verification environments, and developing scalable code using UVM. Strong scripting skills, software engineering expertise, knowledge of object-oriented programming, and proficiency in test bench development processes are required. Effective communication, teamwork, problem-solving skills, planning, and estimation abilities are also essential. Leadership and mentoring experience, familiarity with multiprocessing microarchitecture, bus protocols, and formal verification test benches are advantageous for this role. In summary, the successful candidate will be a proactive team player with a strong technical background, exceptional problem-solving skills, and a dedication to delivering high-quality results within the specified timelines.,

We are hiring 8+ years of hands-on DV experience in System Verilog/UVM.

Hiring Now: Design Verification Engineers (Multiple Openings) Locations: Bangalore & Pune Experience: 4+ to 18 Years Notice Period: Immediate to 30 Days Email: prabhu.p@acldigital.com WhatsApp: 8754387484 Current Openings 1 Senior Design Verification Engineer 10+ Years (Bangalore) – 1 Position Strong expertise in SystemVerilog (SV) and UVM-based verification Mandatory : Experience with ARM Coresight Debug subsystem Strong debugging and problem-solving skills 2 Design Verification Engineer – 5+ Years (Bangalore) – 2 Positions Proficient in SystemVerilog (SV) and UVM Preferred : ARM Coresight Debug subsystem knowledge Strong debugging expertise required 3 Design Verification Engineer – 8+ Years (Bangalore) – 2 Positions Solid experience with SV and UVM Mandatory : CSI/DSI Protocol knowledge Excellent debugging capabilities 4 Design Verification Engineer – 8+ Years (Pune Preferred / Bangalore) – 2 Positions Expertise in SystemVerilog (SV) and UVM Mandatory : Experience with Memory Controller or Cache Strong debug experience is essential Why Join ACL Digital? Work on cutting-edge SoC & IP designs with global semiconductor leaders Opportunity to contribute across leading technology nodes Fast-paced, innovation-driven culture with career growth opportunities Interested candidates can apply now by sharing their CV to prabhu.p@acldigital.com or WhatsApp 8754387484 .

Hi, Greetings from Thales India Pvt Ltd.....! We are hiring for Technical Lead - Design Verification (SV UVM) for our Engineering competency center for Bangalore location. Thales India Engineering Competency Center in Bangalore is seeking Technical Lead /Senior Technical Lead role to be part of AVS/FLX FPGA design and development team. In this role, you will be responsible for FPGA Validation & Verification for Avionics products and solutions. Responsibilities includes development of Test strategy, Virtual Verification Procedures, Test bench, BFMs, Monitors, Checkers & Virtual Verification Report as per DO254 guidelines. Qualifications: B.Tech/B.E or Masters in Electronics & Communication or equivalent with 8 to 12 years of relevant experience. Working experience in Defence\military\Aerospace products development is desirable Location: Thales India Private Limited, Richmond Town, Bengaluru, Karnataka 560025. Required Skills: Mandatory: Hands on in FPGA device Validation and Verification methodologies and processes. Experience in developing verification strategies and creating test plan based on requirements. Hands on Virtual Verification Environment development using VHDL and System Verilog/UVM Should be experienced in BFM development, monitors, checkers and Test case development using VHDL and SV/UVM Hands on with physical verification methodologies for various FPGA devices Good experience in Requirements Capture, developing Design Specification, Detailed design, Test procedure, Test report & other technical artefacts. Hands on experience in performing simulations using the Questasim tool. Should be hands on with configuration management tools such as GIT, BIT Bucket, DOORS, GIT/BIT Bucket/ REQTIFY/DOORS Good experience in RTL Design using VHDL, FPGA Implementation, Testing, Integration and delivery of FPGA based hardware systems for Defense\military\Aerospace Applications. Experience in any scripting language for automation, such as Python, Perl or TCL Experienced with Jenkins for continuous integration and automation of test and build processes. Capable of independently managing project planning, estimation, scheduling, technical risk identification and mitigation. Experience in Intel, Microchip or Xilinx based FPGA/PLD will have added advantage Experience in Bus Interfaces - A818, A429, SPI/UART/I2C, PCIe, AXI4, A664, LVDS, DDRx Should be experienced with environment to work in a cross-functional and multi-national global team. Expected to be Familiar: Experience in FPGA validation and verification in line with DO-254 process Experience in FPGA Implementation Tools (XILINX Vivado/ALTERA Libero SoC/ ALTERA Quartus). Experience in JIRA (Project / Issue management) Experience in handling Lab equipment (Logic Analyzer, Oscilloscope, Function Generators, JTAG, and In-circuit de-buggers).

Verification Engineer Location: Bengaluru Experience: 3+ Years Employment Type: Full-time Job Responsibilities: Create and carry out detailed plans to verify SoC systems. Design and manage test benches using SystemVerilog and UVM. Test the functionality, performance, and low-power aspects of designs. Identify and fix any design or verification problems on your own. Work with high-speed communication protocols like AXI, PCIe, Ethernet, CXL, and UCIe. Make sure that the design is thoroughly tested and follows the specifications. Skills Required: At least 3 years of experience in verifying SoC systems. Strong knowledge of SystemVerilog, UVM, and scripting languages like Python or Perl. Experience with simulation tools like VCS, Cadence, or Synopsys. Good understanding of communication protocols like AXI, PCIe, and Ethernet. Good problem-solving and analytical skills. Preferred Skills: Experience with UCIe (Universal Chiplet Interconnect Express) protocol is a plus. Interested candidates can share their resume to priya@maxvytech.com

SENIOR VERIFICATION ENGINEER- SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). The primary focus of this role will be on Ethernet protocol verification, ranging from 100G to 800G standards. Key Responsibilities: Ethernet Protocol Expertise Demonstrate expertise in Ethernet standards, encompassing 100G to 800G. In-depth knowledge of specific standards, including 100GE (cl45, cl49, CL82, CL91, CL119), 200GE, 400GE (cl161, cl116), and 800GE (802.df/800ETA). Proficiency in PTP 1588 standard and various Ethernet frame types. Competence in packet insertion/extraction techniques. (Additional knowledge of AXI protocol would be considered an advantage) UVM/SV Proficiency Showcase strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Architectural Skills Proven ability to architect, build, and maintain a comprehensive verification stack. Test Development Extensive experience in developing a set of regression tests for verification purposes. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). Excellent understanding of Ethernet protocols, ranging from 100G to 800G. Proficiency in PTP 1588 standard and various Ethernet frame types. Experience with packet insertion/extraction techniques. Knowledge of AXI protocol (preferred). Proven ability to architect, build, and maintain verification stacks. Demonstrated expertise in developing a comprehensive set of regression tests. If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of cutting-edge technology, we encourage you to apply. Join our dynamic team and contribute to the advancement of next-generation technologies. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience Level: Over 4 years Location: Bangalore Skills: Proficiency in SystemC, C++, and SV/Verilog, coupled with hands-on coding experience in these languages. Strong aptitude for debugging and effective communication. Familiarity with scripting languages (desirable). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience Level: 8+ years Location: Bangalore/Hyderabad Skills: Profound expertise in MACSec and Ethernet technologies. MACSec (Media Access Control Security): Proficient in point-to-point security implementation on Ethernet links, adhering to the IEEE 802.1AE-2018 standard. IPsec (Internet Protocol Security): Skilled in establishing security between two devices across an Internet Protocol network. Hands-On Knowledge: Proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), with practical experience in their application. Testbench Development: Demonstrated experience in developing comprehensive Test Benches (TB) and individual verification components. Communication and Leadership: Possesses excellent communication skills and adept at leading and coordinating teams effectively. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation). Key Responsibilities: IP and SOC Verification Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate strong knowledge of SystemVerilog and Universal Verification Methodology for efficient and effective verification processes. Gate-Level Simulation (GLS) Proficiency in Gate-Level Simulation is a mandatory requirement for this position. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Proficiency in Gate-Level Simulation (GLS). If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of integrated circuits, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory). Key Responsibilities: IP and SOC Verification Perform comprehensive IP and SOC verification to ensure the reliability and functionality of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate a strong understanding of SystemVerilog and Universal Verification Methodology for efficient verification processes. CDP, GDP, DFT DV Expertise Possess expertise in Compressed Data Pattern (CDP) and Generic Data Pattern (GDP) methodologies. Proficiency in Design for Test in Design Verification (DFT DV) techniques, including JTAG, MBIST, SCAN, PG, and PM. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong knowledge of SystemVerilog (SV) and Universal Verification Methodology (UVM). Expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST, SCAN, PG, and PM. If you are a talented Design Verification Engineer with a deep understanding of IP and SOC verification, as well as specialized expertise in CDP, GDP, and DFT DV methodologies, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Number of Open Positions4 Experience: 4+ years Location Hyderabad : We are looking for a highly skilled and experienced Gate-Level Simulation Engineer to join our team. The ideal candidate should have a minimum of 4 years of experience and possess a strong background in gate-level simulation (GLS). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is essential for this role. Key Responsibilities: Collaborate with cross-functional teams to define and execute gate-level simulation test plans. Develop and implement gate-level simulation strategies for complex digital designs. Conduct gate-level simulations to verify the functionality and performance of digital designs. Work closely with design and verification teams to identify and resolve issues at the gate level. Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process. Ensure compliance with industry standards and best practices in gate-level simulation. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 4+ years of experience in gate-level simulation. Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Prior experience in gate-level simulation is essential. Familiarity with gate-level simulation tools and methodologies. Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work in a dynamic and fast-paced environment. If you are a motivated and experienced Gate-Level Simulation Engineer with a strong background in SV, UVM, and a passion for ensuring the quality and reliability of digital designs at the gate level, we encourage you to apply for this position. Join our team and contribute to the success of our cutting-edge projects. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaHyderabad